Two methods used for judging feedback and calculating loop gain respectively in actual circuits are presented in the paper. These methods are intuitive and useful for analysis and design of electronic circuits in actuality. These two methods are proved using signal flow chart. The analysis and design of a buffer is presented as an example. The simulation results show that the phase margin of the buffer is 50 Deg after compensation.

A novel 4-bits 10GS/s ADC is presented in the paper The ADC combines the time-interleaved and double-sampling techniques for the first time. Because of the use of double-sampling technique, the ADC needs only the half of the clocks of the traditional time-interleaved ADC. The design of the ADC in 180nm CMOS process technology is described in detail in the paper. The stimulation results show that the SFDR of the ADC achieves 37.68dB at 10GS/s.