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1-4 of 4
Paul Paret
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Proceedings Papers
Ramchandra M. Kotecha, Andriy Zakutayev, Wyatt K. Metzger, Paul Paret, Gilberto Moreno, Bidzina Kekelia, Kevin Bennion, Barry Mather, Sreekant Narumanchi, Samuel Kim, Samuel Graham
Proc. ASME. InterPACK2019, ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, V001T06A017, October 7–9, 2019
Paper No: IPACK2019-6453
Abstract
Gallium oxide is an emerging wide band-gap material that has the potential to penetrate the power electronics market in the near future. In this paper, a finite-element gallium oxide semiconductor model is presented that can predict the electrical and thermal characteristics of the device. The finite element model of the two-dimensional device architecture is developed inside the Sentaurus environment. A vertical FinFET device architecture is employed to assess the device’s behavior and its static and dynamic characteristics. Enhancement-mode device operation is realized with this type of device architecture without the need for any selective area doping. The dynamic thermal behavior of the device is characterized through its short-circuit behavior. Based on the device static and dynamic behavior, it is envisioned that reliable vertical transistors can be fabricated for the power electronics applications.
Journal Articles
Darshan G. Pahinkar, Lauren Boteler, Dimeji Ibitayo, Sreekant Narumanchi, Paul Paret, Douglas DeVoto, Joshua Major, Samuel Graham
Journal:
Journal of Electronic Packaging
Article Type: Research-Article
J. Electron. Packag. December 2019, 141(4): 041001.
Paper No: EP-18-1031
Published Online: May 8, 2019
Abstract
With recent advances in the state-of-the-art of power electronic devices, packaging has become one of the critical factors limiting the performance and durability of power electronics. To this end, this study investigates the feasibility of a novel integrated package assembly, which consists of copper circuit layer on an aluminum nitride (AlN) dielectric layer that is bonded to an aluminum silicon carbide (AlSiC) substrate. The entire assembly possesses a low coefficient of thermal expansion (CTE) mismatch which aids in the thermal cycling reliability of the structure. The new assembly can serve as a replacement for the conventionally used direct bonded copper (DBC)—Cu base plate—Al heat sink assembly. While improvements in thermal cycling stability of more than a factor of 18 has been demonstrated, the use of AlSiC can result in increased thermal resistance when compared to thick copper heat spreaders. To address this issue, we demonstrate that the integration of single-phase liquid cooling in the AlSiC layer can result in improved thermal performance, matching that of copper heat spreading layers. This is aided by the use of heat transfer enhancement features built into the AlSiC layer. It is found that, for a given pumping power and through analytical optimization of geometries, microchannels, pin fins, and jets can be designed to yield a heat transfer coefficients (HTCs) of up to 65,000 W m −2 K −1 , which can result in competitive device temperatures as Cu-baseplate designs, but with added reliability.
Proceedings Papers
Proc. ASME. InterPACK2018, ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, V001T04A006, August 27–30, 2018
Paper No: IPACK2018-8276
Abstract
Sintered silver-based bonded interfaces are a critical enabling technology for high-temperature, compact, high-performance, and reliable wide-bandgap packages and components. High-pressure (∼40 MPa) sintered silver interfaces have been implemented commercially, most notably the commercial products offered by Semikron. To reduce manufacturing complexity, there is significant industry interest in pressure-less sintered silver interfaces. To this end, current formulations of sintered silver paste are comprised of purely nano-sized silver particles or a combination of nano- and micro-sized silver particles/flakes. It is essential to quantify the mechanical properties and determine the reliability of these interfaces prior to use in automotive power electronics applications. In this paper, research efforts at the National Renewable Energy Laboratory, in collaboration with Virginia Polytechnic Institute and State University and an industry partner, in optimizing the synthesis procedure and mechanical characterization of sintered silver double-lap samples are described. These double-lap samples were synthesized using pressure-less sintering techniques. Shear testing was conducted at multiple temperatures and displacement rates on these samples sintered using two types of sintered sintered silver pastes, one of them consisting of nano-silver particles and the other a hybrid paste or a combination of nano- and micron-sized silver flakes, employed in a double-lap configuration. Maximum values of shear stress obtained from the characterization study are reported.
Proceedings Papers
Proc. ASME. InterPACK2013, Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes, V001T05A004, July 16–18, 2013
Paper No: IPACK2013-73143
Abstract
In automotive power electronics packages, conventional thermal interface materials such as greases, gels, and phase change materials pose bottlenecks to heat removal and are also associated with reliability concerns. There is an industry trend towards high thermal performance bonded interfaces. However, due to coefficient of thermal expansion mismatches between materials/layers and resultant thermomechanical stresses, adhesive and cohesive fractures could occur, posing a problem from a reliability standpoint. These defects manifest themselves in increased thermal resistance in the package. The objective of this research is to investigate and improve the thermal performance and reliability of emerging bonded interface materials for power electronics packaging applications. We present results for thermal performance and reliability of bonded interfaces based on thermoplastic (polyamide) adhesive, with embedded near-vertical aligned carbon fibers, as well as sintered silver material. The results for these two materials are compared to conventional lead-based (Sn63Pb37) bonded interfaces. These materials were bonded between 50.8-mm × 50.8-mm cross-sectional footprint silicon nitride substrates and copper base plate samples. Samples of the substrate/base plate bonded assembly underwent thermal cycling from −40°C to 150°C according to Joint Electron Devices Engineering Council standard Number 22-A104D for up to 2,000 cycles. The dwell time of the cycle was 10 minutes and the ramp rate was 5°C/minute. Damage was monitored every 100 cycles by acoustic microscopy as an indicator of an increase in thermal resistance of the interface layer. The acoustic microscopic images of the bonded interfaces after 2,000 thermal cycles showed that thermoplastics with embedded carbon fibers performed quite well with no defects, whereas interface delamination occurred in the case of sintered silver material. Both these materials showed a superior bond quality as compared to the lead-based solder interface even after 1,000 thermal cycles.