A thermo-mechanical analysis is carried out on a stacked die package having through silicon via technology to study the overall reliability of the package due to varying aspect ratio (size and shape) of through silicon vias, silicon die thickness, underfill thickness and underfill material properties. Through silicon via technology is one of the most rapidly developing technologies in the semiconductor industry and assures the development for the continued role of Moore’s law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor and cost reduction of the package. A three dimensional finite element model of a stacked package that consists of stacked dice using through silicon vias, solder interconnect, underfill, substrate and PWB is solved numerically to assess the reliability of the overall stacked package. In this analysis, stress free temperature for stacked package is kept at 125°C while room temperature is 25°C to carry out the simulation of the stresses post cure cool down of the stacked package. Stresses are calculated at the die as well as interfaces between underfill and die and underfill and substrate to assess the reliability of the overall package. A parametric study of critical geometric parameters such as aspect ratio, thickness of silicon die and underfill thickness and process parameters is carried out to minimize the maximum stresses on the overall stacked package. Recommendations are provided with respect to controlling the critical parameters such as aspect ratio, silicon thickness, underfill thickness and varying the underfill material properties (E and α) to improve the overall reliability and strength of the package.

Since the advent of the transistor and integrated circuit, the performance of electronic equipment has increased significantly while footprint of systems at all levels continues to decrease. Recently, the number of transistors on a high end microprocessor has exceeded a billion. All of the above has necessitated considerable improvement in cooling technology and associated reliability. Heat sinks play an important role in cooling technology by providing an increased surface area to dissipate heat. While there has been a great deal of work related to the thermal performance of heat sinks, there has not been a corresponding effort in studying the mechanical related reliability issues of the heat sinks. Previous work has been done to study the effect of adhesively bonded heat sink on the mechanical reliability of a two-layer wire bonded plastic ball grid array (WB-PBGA) package. Stresses induced in the package have been computed for a wide range of values of the adhesive mechanical properties and Young’s modulus. Variation of interfacial peel and shear stresses at the interface between the mold compound and the adhesive and between the adhesive and the heat sink have been qualitatively assessed for propensity of interfacial de-lamination along these two interfaces. In this paper a stress analysis of described package is carried out to study the effect of heat sink assembly on the mechanical reliability of the package. A three dimensional finite element model of WB-PBGA package and Printed wiring board (PWB) is solved numerically to predict the stresses induced and assess their impact on the mechanical integrity of the die and package due to the heat sink assembly. Die and C4 interconnect stresses are examined to evaluate package reliability. Stresses induced within the die and C4 interconnect are examined for different heat sink materials and variation of force developed by heat sink attachments such as clip and screw type has been examined. Finally recommendations will be made regarding choice of heat sink material and clipping force for overall heat sink assembly design. The modeling utilizes a solid model for geometry creation and a finite element commercial program for simulation.

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.