Metal-assisted chemical etching (MacEtch) of silicon shows reliable vertical anisotropic wet etching only in single-crystal silicon, which limits its applications to a small number of devices. This work extends the capabilities of MacEtch to polysilicon which has potential to enable high-volume and cost-sensitive applications such as optical metasurfaces, anodes for high capacity and flexible batteries, electrostatic supercapacitors, sensors, nanofluidic deterministic lateral displacement devices, etc. This work presents a MacEtch of polysilicon that produces nanostructure arrays with sub-50 nm resolution and anisotropic profile. The three demonstrated structures are pillars of 5:1 aspect ratio and 50 nm spacing for comparison to single crystal silicon MacEtch literature, pillars of 30 nm spacing, and a diamond pillar array with sharp corners to establish resolution limits of polysilicon MacEtch.
Metal-assisted chemical etching (MacEtch) is a wet-etch technique that is uniquely suited to etch high-resolution high-aspect-ratio nanostructures with no measurable sidewall roughness in single-crystal silicon. However, for several high-volume and cost-sensitive applications (such as optical elements for AR/VR, novel batteries, and capacitors), single-crystal silicon is not a substrate of choice. These applications require parallel processing of many unit products on large substrates to reduce the average cost per product. Roll-to-roll processing is ideally suited for such applications. However, single-crystal silicon is not available on roll substrates and instead requires transferring to flexible substrates to demonstrate flexible silicon devices [1,2]. In this context, the ability to perform high-quality MacEtch on polysilicon (poly-MacEtch) could be highly relevant, since the roll-to-roll deposition of polysilicon is feasible and economically viable [3,4]. Outside of MacEtch on roll substrates, poly-MacEtch could potentially enable H3 nanostructures on nonsilicon substrates such as glass (especially display-grade glass which has applications in the AR/VR space). Poly-MacEtch could also be used to fabricate polysilicon-based nanostructures on top of existing semiconductor devices, which could have applications in the emerging space of Heterogenous Integration and Advanced Packaging.
Metal-assisted chemical etching of polysilicon is currently in a nascent state [5–7]. Kim et al. have attributed the poor quality of polysilicon MacEtch to the presence of grain boundaries in polysilicon, which can increase the tendency of the catalyst to wander in uncontrollable ways during the etch . Their proposed self-anchored catalyst approach can produce polysilicon vias down to ∼400 nm diameter (1-μm pitch). However, the 400 nm diameter vias seem to have a large amount of taper, and it seems unlikely that this method would scale well to sub-100 nm high-aspect-ratio nanostructures. Li et al. achieved a high aspect ratio and structural profile of microscale polysilicon features (holes of 29-μm width and 58-μm depth) with electric bias-attenuated metal-assisted chemical etching (EMaCE)  and attributed bias application as an essential factor in resulting polysilicon etch. However, dependence on bias application may impede the commercial viability of EMaCE in industrial fabrication ecosystems. Additionally, MacEtch of polycrystalline silicon should be capable of producing nanoscale features in order to be competitive against conventional fabrication methods that cater to both nanoscale and microscale benchmarks (Fig. 1).
In this paper, we provide the first known demonstration (to the best of our knowledge) of high-quality high-resolution (sub-50 nm spacing) high-aspect-ratio MacEtch of polysilicon, enabled by the following three process steps:
Planarization of deposited polysilicon, to levels that allow for high-resolution patterning.
High-resolution patterning using nano imprint lithography (NIL).
High-aspect-ratio etching of NIL patterns in polysilicon using a MacEtch process.
We will refer to the combination of the above three process steps as poly-MacEtch, in subsequent text.
2 Experimental Methods
In this work, we have utilized 1-μm-thick undoped polysilicon, deposited on polished 〈100〉 single-crystal silicon p-type wafers, for demonstration of poly-MacEtch. Polysilicon was deposited with low-pressure chemical vapor deposition (LPCVD) at 620 °C, followed by chemical mechanical polishing (CMP) of the film. For comparison purposes, single-crystal MacEtch samples were also fabricated, using 〈100〉 p-type silicon wafers, with the MacEtch performed using a previously reported technique employing gold as the MacEtch catalyst . All experiments followed the same overall process flow, depicted in Fig. 2. It is worth noting that in future roll-to-roll processing of polysilicon, a straightforward CMP process would not be possible. Instead, one could utilize inkjet-based planarization techniques, such as the one described in Khusnatdinov et al. .
2.1 Resist Patterning.
Wafers with polished polysilicon films were prepared for patterning by a spin coat of BT49 adhesion layer. Wafers for all experiments were patterned using jet-and-flash imprint lithography (J-FIL), which is a form of NIL. An Imprio-1100 wafer-scale J-FIL tool was utilized for this purpose (Molecular Imprints, TX) with AZ 5209 E resist. The NIL template was fabricated by a commercial photomask vendor, Dai Nippon print (DNP) of Japan. J-FIL produces a residual layer that was removed with an oxygen and argon-based reactive ion etch process.
2.2 Catalyst Deposition.
Thin films of titanium and gold were deposited using a vacuum-based electron-beam evaporator (CHA Industries, Inc.). Gold functions as the catalyst for MacEtch process. Titanium acts as an adhesion promoter to prevent gold delamination at the beginning of the etch. The best results were achieved with titanium thicknesses between 0.5 and 2 nm, and gold thicknesses between 10 and 15 nm. Deposition of titanium was conducted at a rate of 0.1 Å/s, and of gold at a rate of 0.4 Å/s, both at a pressure of ∼5 × 10−6 torr.
2.3 Metal-Assisted Chemical Etching.
MacEtch etchants used in this work comprise hydrofluoric acid (HF), hydrogen peroxide (H2O2), and deionized (DI) water. MacEtch of polysilicon was performed using an etchant composition of 4 HF: 1 H2O2: 4 H2O (by volume). It has been shown in prior works that polysilicon is more prone to spurious porosity during MacEtch compared to single-crystal silicon . A high concentration of H2O2 in the MacEtch etchant is generally associated with porosity during etching [10–12]. Therefore, to counter the higher-than-usual tendency of polysilicon to exhibit porosity during MacEtch, H2O2 concentrations were kept relatively low. The etch was performed at room temperature on an acid bench located in a class 100 cleanroom.
2.4 Postetch Characterization.
Cross-sectional scanning electron microscope (SEM) characterization was performed using a ZEISS Neon 40 SEM, and top-down SEM using a Scios 2HiVac dual beam SEM system. Sample preparation of polysilicon samples includes deposition of 2 nm gold-palladium alloy, using an Emitech Sputter Coater K575X -SEM, to enhance image fidelity. The ZEISS Neon 40 SEM and Emitech Coater were used in the Microelectronics Research Center at J.J. Pickle Research Center, The University of Texas at Austin. The Scios SEM system was used at Texas Materials Institute, The University of Texas at Austin.
3.1 Polysilicon Pillars With 50 nm Spacing.
Figure 3 below shows pillars with an aspect ratio of 5:1, created in polysilicon, using NIL-based patterning, and with our existing process-of-record for single-crystal silicon modified for polysilicon. Circular-cross section pillars were chosen for polysilicon MacEtch, to allow comparison with our prior work on single-crystal silicon MacEtch, which utilized similar pillar arrays [8,13–15].
3.2 Polysilicon Pillars With 30 nm Spacing.
Figure 4 shows the fabrication of polysilicon pillars of 30 nm spacing, which required a modified imprint step (creating a template of inverse tone) that increased the diameter of pillar resist caps from their initial value of 150 nm to 170 nm. This modification seems to introduce surface defects in the patterned catalyst layer, which results in vertical striations after MacEtch (Fig. 5). This occurred in single-crystal silicon as well (Fig. 5(b)). Therefore, it seems reasonable to assume that these striations are an artifact of the modified imprint process, and not of the polysilicon MacEtch process.
3.3 Diamond-Shaped Polysilicon Pillars.
Pillars with diamond-shaped cross section were fabricated to investigate the resolution limits of polysilicon MacEtch, and to further compare MacEtch etch quality between polysilicon and single-crystal silicon. It is worth noting that etching of diamond-shaped pillars also results in the creation of complementary circular-shaped-holes (that are connected using tethers). Thus, the ability to etch diamond-shaped pillars has important implications for etching high-aspect-ratio vias and holes, for instance, for DRAM structures. Etching isolated holes using MacEtch is generally challenging since isolated catalyst islands are subject to drift. Additionally, etchant transport becomes increasingly problematic with increasing etch depth. Holes in polysilicon have also been etched with MacEtch previously. However, such structures exhibit common etch defects such as profile taper and sidewall roughness [6,7]. Figure 6 depicts the process flow for fabricating diamond-shaped pillars and tone inversion to circular holes, and Fig. 7 shows SEM images of the fabricated diamond-shaped pillars.
4.1 Planarization of Polysilicon.
In order to enable patterning using NIL, CMP of polysilicon was incorporated to minimize the surface roughness of the deposited film. As-deposited polysilicon films often have high surface roughness, reportedly up to 580 Å Ra for 11 μm thick films , which can cause defective NIL patterning. Although CMP suitably reduced the extent of NIL defects, as defects did not arise in initial NIL patterning, the existing roughness of the polysilicon film negatively affected the morphology of NIL resist caps after residual layer etch. Defects in resist cap morphology led to defects in the MacEtch catalyst layer, which finally lead to vertical sidewall striations after MacEtch. This effect of CMP on polysilicon etching, wherein CMP reduces but does not completely eliminate sidewall striations, is seen in reactive ion etch as well .
4.2 Patterning of Resist Caps.
An important difference between this work and prior works on polysilicon MacEtch is the type of patterning technique utilized [5,6]. This work utilized commercial-grade NIL, which allowed us to create patterns with long-range order as well as good critical dimension uniformity in the resulting nanostructures. Prior works have shown only one of the said two characteristics, but not at the same time.
4.3 MacEtch at the Interface Between Polysilicon and Single-Crystal Silicon.
To further investigate poly-MacEtch, a longer etch was conducted to examine MacEtch at the interface of polysilicon and silicon. Pillars of 150 nm spacing did not maintain structural integrity and broke at the apparent material interface. However, fins of 150 nm width were etched successfully. SEM characterization of the resulting polysilicon-silicon stack showed a tapered polysilicon profile, as shown below (Fig. 8).
The taper likely does not result from the MacEtch etch itself, but rather from intrinsic residual stresses near the material interface. It has been shown that the internal stresses of polycrystalline thin films are highly dependent on film deposition conditions . The amount of taper near the interface could potentially be reduced by performing LPCVD deposition of polysilicon at a higher temperature or by a posted high temperature anneal. For instance, an anneal of 1100 °C has been shown to reduce the intrinsic stress of polysilicon films to near zero from 350 MPa compressive intrinsic stress . Note that in this work, LPCVD polysilicon films were deposited at a relatively low temperature of 620 °C for parallel comparison to preceding MacEtch techniques for polysilicon.
In this paper, we have extended our prior work on high-resolution high-aspect-ratio nanostructures of single-crystal silicon to polycrystalline silicon. We have shown reliable etching of high-aspect-ratio structures in polysilicon that is not compromised by crystal grain boundaries, and that do not exhibit spurious porosity (which is achieved through careful tuning of the etch chemistry). The etch is enabled by the following three techniques:
Reduction of surface-roughness of as-deposited polysilicon to levels that allow high-resolution patterning.
High-resolution patterning using NIL.
High-aspect-ratio etching of NIL patterns in polysilicon using a MacEtch process.
This work, combined with high-resolution patterning capabilities of NIL in roll substrates , and inkjet-based planarization techniques  to reduce surface roughness, could potentially open new avenues for deploying MacEtch in roll-to-roll format for a variety of high-volume industrial applications that require high-resolution high-aspect-ratio nanostructures with no measurable sidewall roughness, ranging from optical elements for AR/VR, novel batteries and capacitors, etc. It is worth noting that NIL is likely the only practical and cost-effective method for patterning arbitrary features at sub-50 nm feature sizes on roll substrates. Comparable optical techniques such as photolithography (including EUV), and interference lithography require high substrate site-flatness for high-resolution image formation on the patterned substrate (proportional to λ/NA2; ∼150 nm for 0.33 NA EUV) (20). Such high levels of substrate site-flatness are not available on roll substrates. Also, these photolithography techniques have small exposure areas (∼50–75 mm2) while nano-imprint has been shown to work across meter-wide roll substrates .
One area for future work includes improving the deposition conditions of polysilicon. High-aspect-ratio polysilicon structures are prone to profile defects, such as taper. Such defects likely arise from internal residual stresses in polysilicon during deposition. High-temperature processing can remove these internal residual stresses [18,21]. However, this might not be an option for a variety of applications that are limited to low-temperature processing due to the type of roll substrate employed (polymers roll substrates, for instance,) or dopant diffusion in semiconductor integrated circuit applications. Thus, more work is required in understanding how to mitigate such stresses for polysilicon deposited at low temperatures with low residual stress. This should include the expansion of poly-MacEtch to low-temperature deposition processes, such as hot wire chemical vapor deposition  or PECVD [23,24].
This work was partly conducted at the Texas Nanofabrication Facility supported by NSF grant NNCI-1542159 and partly conducted at the NASCENT Center supported by NSF grant NNCI-1542159. This work was in part funded by the Cockrell School of Engineering, and by the Cockrell Family Regents Endowed Chair #7 funds. Any opinions, findings and conclusions, or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
National Science Foundation (Grant No. NNCI Award 1542159; Funder ID: 10.13039/100000001).
Cockrell School of Engineering.