Here explored is a method by which designers can use the tool of topology optimization to numerically improve barriers to reverse engineering. Recently developed metrics, which characterize the time (T) to reverse engineer a product, enable this optimization. A key parameter used in the calculation of T is information content (K). The method presented in this paper pursues traditional topology optimization objectives while simultaneously maximizing K, and thus T, in the resulting topology. New aspects of this paper include algorithms to (1) evaluate K for any topology, (2) increase K for a topology by manipulating macroscale geometry and microscale crystallographic information for each element, and (3) simultaneously maximize K and minimize structural compliance (a traditional topology optimization objective). These algorithms lead designers to desirable topologies with increased barriers to reverse engineering. The authors conclude that barriers to reverse engineering can indeed be increased without sacrificing the desirable structural characteristic of compliance. This has been shown through the example of a novel electrical contact for a consumer electronics product.

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