Surface Quality and Contamination on Si Wafer Surfaces Sliced Using Wire-Electrical Discharge Machining

In the past, studies on wire-electrical discharge machining (EDM) of Si wafers have often focused on the effect of energy-related parameters on various wafer characteristics. However, comprehensive treatment on analyzing the effect of non-energy parameters of the Si wafer slicing process is not available thus far. This work, therefore, presents an extensive experimental work considering the parameters like wire tension (WT), wire feed rate (WF), and dielectric flushing pressure (W_aP) on crucial wafer characteristics such as wafer-thickness and its uniformity, thermal damage, wire material contamination on wafer surfaces, and surface quality. A total of 72 experiments were performed at low and high servo voltage (SV) conditions. The sliced wafers were characterized by SEM, EDAX, and ICP-AES techniques. Ultrathin wafers with a uniform thickness of ∼107 µm were sliced at high SV conditions, while a lower thermal damage (∼10 µm) with low wire contamination was observed during low SV conditions. The percentage of contamination was further found to decrease with an increase in WT, WF, and W_aP during low SV conditions. The wafer surface etching showed the diffusion of contaminates like Cu/Zn up to a depth of 25–30 µm. The wafer surface roughness in the middle section has always been observed to be poor due to short-circuiting and arcing within that zone.