Active control of the die-level temperature is desirable during production testing of high power microprocessors, so as to ensure accurate performance classification. Such control requires that the controlling thermal load time-lead the dissipated thermal load and that it be modulated to account for the distributed thermal capacitance and resistance of the device packaging. The analysis in this paper demonstrates fundamental limits of temperature control for typical devices under test conditions. These limits are identified for specified control power to die power ratios. The effects of test sequence design and device package design on the temperature control limits are also examined. The theory developed can be applied to any thermal control problem where a conductive medium separates the control source from the location where control is desired.

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