In this work, a rapid and low-cost accelerated reliability test methodology which was designed to simulate mechanical stresses induced in flip–chip bonded devices during the thermal cycling reliability test under isothermal conditions, is introduced and demonstrated using power device analogous test chips. By stressing these devices in a controlled environment, mechanical stresses become decoupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device relevant, flip–chip solder interconnects while monitoring for failure. Herein, finite element analysis (FEA) is used to extract various damage metrics of different solder materials, including PbSn37/63, SAC305, and nanosilver, in both thermal operation and the introduced alternative mechanical testing conditions. Plastic work density and strain are calculated in the critical solder interconnects as factors that indicate the amount of the damage accumulation per cycle during the mechanical cycling, thermal cycling, and power cycling tests. The number of cycles to failure for each test was calculated using the fatigue life model developed by Darveaux for eutectic PbSn solder, while for SAC305 Syed's method was used, and for nanosilver, the Knoerr et al. equations are applied. The effects of environmental temperature and shearing force frequency were studied for the mechanical cycling reliability test, where a modified Norris–Landzberg equation for mechanical cycling tests was explored using the simulation results. Finally, comparing the mechanical cycling with the equivalent thermal cycling and power cycling demonstrated a significant reduction in required test duration to achieve a reliability estimation.

When two thin plates or layers are bonded together, an extremely thin bond layer of third material exists between the two layers. This research work examines the effect of bond layer on the interfacial shearing and peeling stresses in a bimaterial model. Earlier papers on this topic are based on several mutually contradictory expressions for the shear compliance of the bond layer. This paper is aimed at resolving this ambiguity and presents derivation of shear compliance on a rational basis. A numerical example is carried out for a silicon-copper system with a gold-tin solder bond layer. The results obtained are likely to be useful in interfacial stress evaluation and physical design of bimaterial assemblies used in microelectronics and photonics applications.

Reliable drop test simulations of electronic packages require reliable material characterization of solder joints. Mechanical properties of lead-free solder were here experimentally investigated for both monotonic and cyclic loading at different strain rates. With regards to the observed complex material behavior, the nonlinear mixed hardening Armstrong and Frederick model combined with the Perzyna viscoplastic law was chosen to fit the experimental data. This model was subsequently implemented into a commercial finite element code and used to simulate drop tests. Actual drop test experiments were conducted in parallel and experimental results were compared to simulations. Prediction discrepancies were analyzed and explanations suggested.

In this paper, the packaging aspects of directly modulated laser (DML) modules are investigated using detailed electromagnetic (EM) simulations. The packaging influences of the laser module are specified in two parts as RF connector and optoelectronic subsystem. By carefully optimizing the package structure, the simulation results show that the insertion loss of the proposed module is less than 1 dB up to 40 GHz. Then, a DML module is packaged and measured based on the optimized package scheme. A resonance free bandwidth of approximately 20 GHz is obtained with a 3 dB bandwidth of about 15 GHz.

Polymeric material has been applied in electronic product extensively, especially for packaging applications, thus thermomechanical analyses for encapsulated structure are frequently encountered. However, modulus and thermally induced strain of polymeric material are not constant, but time- and temperature-dependence. For simplification of the stress constitutive models, particularly for applications on electronic packaging can be found in literature, the time-dependent behavior could be neglected. Otherwise, the property only considered as a function of temperature can achieve time saving and cost down, but to the best of the author’s knowledge, the thermomechanical analysis based on different conservation laws so far has not been studied indeed. Most of the relative studies published in literature are in strain conservation law, and recently strain–stress conservation law was formulated, so-called force-displacement incremental solution. This study has developed a stress-based conservation law regardless of derived strain and strain–stress based conservation laws for stress constitutive models applied in thermomechanical analysis; meanwhile, incorporated cross-link induced residual strain from polymer forming. Furthermore, the nonincrement approach is implemented by a concept of force and moment equilibrium on the flexural stiffness of final stage, and derived for efficiency enhancing. On the other hand, analytical solutions based on different conservation laws for bimaterial plate were utilized to compare with experimental measurements. The results indicate that warpage analysis based on stress conservation law with temperature-dependent property can be more realistically predicted over a range of temperature, whereas a large error can be caused by using approximated CTE or nonconsidering residual strain, especially for temperature above T g .

Potted electronics are becoming more common in precision-guided artillery due to demands for increased structural-robustness. In field artillery applications, the potted electronics are inactive for most of their lifetime. Projectiles may be stored in a bunker without environmental (temperature and humidity) controls for up to 20 years. In contrast, the electronics for most commercial applications tend to be active for most of their lifetime and the operating environment is more predictable. This difference makes the thermal management task for the artillery application challenging. The ability to accurately analyze these designs requires the use of fully coupled thermal-stress transient-analysis with accurate material properties over the full temperature range. To highlight the thermal-stress transient effects, the potted configuration of a typical electronics assembly is analyzed. The thermal analysis indicates that significant stresses can develop in critical locations as a result of temperature cycles. The structural dynamic responses of unpotted and potted assemblies, subjected to gun-launch environments, are also compared. The results indicate that for the potted design, the dynamic response of the processor board is attenuated by the potting material.

Demand for long-term reliability of electronic packaging has lead to a large number of studies on viscoplastic behavior of solder alloys. Various creep models for solder alloys have been proposed. They range from purely empirical to mechanism based models where dislocation motion and diffusion processes are taken into account. In this study, most commonly used creep models are compared with the test data and implemented in ABAQUS to compare their performance in cycling loading. Finally, a new creep model is proposed that combines best features of many models. It is also shown that, while two creep models may describe the same material stress–strain rate curves equally well, they may yield very different results when utilized for cycling loading. One interesting observation of this study is that the stress exponent, n., also depends on the grain size.

Latest electronic component package types are pushing the need to more efficiently remove the dissipated heat using optimized thermal paths going through the printed circuit board (PCB) to reach PCB inner thermal planes. So, to optimize board cooling, the designer has more and more to deal with PCB architecture including high density interconnect (HDI) technology, which relies on small diameter laser drilled micro-vias. Compared with conventional PCB technologies, HDI creates denser interconnect substrates, containing multilevel micro-via structures that play a decisive role in the miniaturization of circuit boards but will exacerbate the component cooling design complexity. To improve the understanding of conventional and future configurations of via structure and their influence on the component thermal performances, a study was leaded on an micro lead frame package, which is now mainstream for both analog and digital functions. For still air conditions, the thermal simulation results show that via and micro-via structures allow to drain more than 90% of the component power through the PCB metallic planes and are mandatory to limit the temperature excess. Thus, the thermal modeling of the latest 3D Integrated Circuit is reinforcing the need to simulate in more thin details its board surrounding architecture as well as its packaging. However, a fine detailed modeling of board layers layout always exceeds the simulation tool capabilities and requires new modeling methodologies able to define the most significant thermal model. Based on DEvelopment of Libraries of PHysIcal models (DELPHI) methodology, the creation of a compact thermal model, compliant to a set of boundary conditions was investigated for a local board area. The thermal behavior prediction, found to be within ± 5% of error, demonstrates the feasibility of extending the boundary condition independence principle to board modeling in order to achieve a more efficient and accurate board cooling optimization.

The significant difference between failure modes of lead-containing and lead-free solder joints under drop impact loading remains to be not well understood. In this paper, we propose a feasible finite element approach to model the cracking behavior of solder joints under drop impact loading. In the approach, the intermetallic compound layer/solder bulk interface is modeled by the cohesive zone model, and the crack driving force in the intermetallic compound layer is evaluated by computing the energy release rate. The numerical simulation of a board level package under drop impact loading shows that, for the lead-containing Sn37Pb solder joint, the damage in the vicinity of the intermetallic compound layer initiates earlier and is much greater than that in the lead-free Sn3.5Ag solder joint. This damage relieves the stress in the intermetallic compound layer and reduces the crack driving force in it and consequently alleviates the risk of the intermetallic compound layer fracturing.

The objective of this study is to predict numerically the optimal spacing between parallel heat generating boards. The isothermal boards are stacked in a fixed volume of electronic package enclosed by insulated lateral walls, and they are cooled by laminar forced convection of air with prescribed pressure drop. In the numerical procedure, governing equations for the solution of forced convection of constant property incompressible flow through one rectangular channel are solved. Resulting flow and temperature fields in each rectangular channel yield the optimal board-to-board spacing by which maximum heat dissipation rate from the package to the air is achieved. Next, generalized correlations for the determination of the maximum heat transfer rate from the package and optimal spacing between boards are derived in terms of prescribed pressure difference, board length, and density and kinematic viscosity of air. Finally, corresponding correlations are compared with the available two-dimensional studies in literature for infinite parallel plates.

Electromigration (EM) in solder joints under high current density has become a critical reliability issue for the future high density microelectronic packaging. This paper presents atomic density redistribution algorithm for predicting electromigration induced void nucleation and growth in solder joints of Chip Scale Package (CSP) structure. The driving force for electromigration induced failure considered here includes the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient, which were neglected in many of the existing studies on electromigration. The simulation results for void generation and time to failure (TTF) are discussed and correlated with the previous test results. EM sensitivity analysis is also performed to investigate the effect of EM parameters and mechanical properties of material on electromigration failure. The simulation results indicated that the atomic density on the activation energy is quite sensitive, and the mechanical material parameters have no impact on EM sensitivity of normalized atomic density.

A fundamental study is carried out to investigate the microstructure and surface treatment possibilities of 304 stainless steel (304SS) substrates. To expose the microstructure, mirror-finished 304SS is applied with a self-mixed etchant containing ammonium sulfite ((NH 4 ) 2 SO 3 ), iron chloride (FeCl 3 ), hydrochloric acid (HCl), and nitric acid (HNO 3 ). Scanning electron microscope (SEM) images exhibit quite clear rocky-wall-like structure. Grain boundaries are clearly observed. Each grain contains many subgrains and the average grain size is 10 μ m. Energy dispersive X-ray analysis determines the composition as 69 wt. % iron (Fe), 19 wt. % chromium (Cr), 10 wt. % nickel (Ni), around 2 wt. % manganese (Mn), and less than 0.08 wt. % carbon (C), which agrees well with the data provided by the manufacturer. Diffraction peaks produced by X-ray diffraction (XRD) are able to correspond to profiles found in XRD database, showing that 304SS has face-centered cubic crystal lattice. The Ni strike technique is used as surface treatment to make 304SS bondable to other metals, such as silver (Ag), copper (Cu), and gold (Au), commonly used in electronic packaging. Cross section SEM images show that thick Ag, Cu, up to 50 μ m, and Au, up to 70 μ m, were successfully plated over the thin Ni layer that was plated on 304SS.

Improvements in thermal interface materials (TIMs) can enhance heat transfer in electronics packages and reduce high temperatures. TIMs are generally composed of highly conductive particle fillers and a matrix that allows for good surface wetting and compliance of the material during application. Two types of TIMs are tested based on the addition of carbon nanotubes (CNTs): one mixed with a commercial TIM product and the other only CNTs and silicone oil. The materials are tested using an in-house apparatus that allows for the simultaneous measurement of temperature, pressure, heat flux, and TIM thickness. Results show that addition of large quantities of CNTs degrades the performance of the commercial TIM, while the CNT-silicone oil mixtures showed improved performance at high pressures. Thickness and pressure measurements indicate that the CNT-thermal grease mixtures are more compliant, with a small increase in bulk thermal conductivity over the range of tested pressures.

Two types of packaged white light emitting diodes in which one has a flat-top (FT) emitting surface and the other is a flat-top-with-lens (FTWL) type are fabricated by using the same leadframe and investigated on their optical properties, such as optical power, luminous efficiency, correlated color temperature (CCT), chromaticity coordinate, and color-rendering index (CRI), as a function of phosphor concentration in silicone encapsulant. It is found out that the optical power, CRI, and CCT decrease steadily as the phosphor ratio increases, while the luminous efficiency increases up to a level and then drops after a certain value of the phosphor ratio for both types of packages. Due to the totally internal reflection (TIR) at the encapsulant-air interface, the FT package shows a 10 ∼ 11 % power (in mW) reduction compared with the FTWL package at the same phosphor concentration. However, it is demonstrated that the FT package provides a more efficient way of utilizing phosphor than the FTWL package based on the same targeted chromaticity coordinates due to the TIR effect inside, resulting in a reduced phosphor usage with a lumen output only about 3% lower than that of the FTWL package.

Computational fluid dynamics (CFD) and artificial neural network (ANN) are used to examine the cooling performance of two electronic components in an enclosure filled with a Cu-water nanofluid. The heat transfer within the enclosure is due to laminar natural convection between the heated electronic components mounted on the left and right vertical walls with a relatively lower temperature. The results of a CFD simulation are used to train and validate a series of ANN architectures, which are developed to quickly and accurately carry out this analysis. A comparison study between the results from the CFD simulation and the ANN analysis indicates that the ANN accurately predicts the cooling performance of electronic components within the given range of data.

The DJOSER analytical thermal solver for multilayer mounting structures has been tested as a useful and friendly tool for the thermal analysis of power electronic devices and their packages, able to replace the onerous programs based on the finite element method (FEM) calculations. The other problem connected with the packaging evaluation is the calculation of the thermally induced stresses and strains in the various layers composing the assembling structures. This paper deals with the first step of the implementation of a thermomechanical solver to be connected with the DJOSER program, which is able to calculate the stresses at the layer interfaces, using the same strategy, i.e., a semianalytical mathematical approach, as well as the same structural models (stepped pyramidal structures and homogeneous layers). The basic theory is briefly exposed and the method is applied to some two-layer virtual structures. The obtained results are compared with those obtained using standard FEM analyses.

In the current study, a network-based resistor model has been developed for thermal analysis of a complex opto-electronic package called small form-factor pluggable device (SFP). This is done using the DEvelopment of Libraries of PHysical models for an Integrated design (DELPHI) methodology. The SFP is an optical transceiver widely used in telecommunication equipments such as switches and routers. The package has a detailed construction and typically has four fixed heat generating sources. The detailed model for the SFP is constructed and calibrated using a natural convection experiment. The calibrated detailed model is used for generating the limited boundary-condition-independent compact thermal model (CTM). Limited boundary-condition-independence, in this case, refers only to a small subset of all “thinkable” boundary conditions that are experienced by the SFP device in practical situations. The commercial optimization tool developed by the DELPHI team, DOTCOMP , is used for generating the compact thermal model. A detailed validation of the CTM of the SFP in real-time applications using FLOTHERM 7.2, a computational fluid dynamics-based thermal analysis software package, is performed. The results show excellent agreement between the results predicted by the SFP CTM with the data from the detailed model. The SFP CTM predicts the junction temperature of the four power-dissipating components and the heat flows through the sides with relative error less than 10%.

As a thermal interface material, thermal grease (TG) has been extensively applied to facilitate heat dissipation in electronic devices. Despite the superior thermal conductivity of diamond, researches on diamond-containing TGs remain rare. In this study, four kinds of TGs in which diamond served as essential filler were prepared and hot disk technique was applied to measure their thermal conductivity k ( TG ) . After two unoverlapped particle sizes were selected, the volumetric filler content, terminal group, and viscosity of a polydimethylsiloxane (PDMS) matrix were modified in sequence. Based on the preferred recipe of a single-filler TG, two double-filler TG series were prepared by retaining the large diamonds and replacing the small ones by Al 2 O 3 or ZnO, respectively. Depending on the content, it was found that diamond was not always the best choice for small filler. The highest k ( TG ) , which was 23 times greater than the original k ( PDMS ) , appeared in a ZnO-containing double-filler grease ( = 3.52 W / mK ) . The prediction for the maximum attainable thermal conductivity was preliminarily supported.