Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder bumps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithic integrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 × 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μ m to 15 μ m, or 10 μ m, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

A molded wafer-level package simulation model was successfully developed for calculating solder ball fatigue life during a temperature cycle test (TCT), revealing that the most crucial factor affecting fatigue life, rather than being the maximal stress in solder balls, is the equivalent strain range in solder balls during the creep effect. Accordingly, in a TCT, the fatigue life of the solder balls, which are located from the outer edge to the center, is negatively correlated with the equivalent strain range; the earliest solder balls to rupture are those located at the outer edges, which have the highest equivalent strain range but not the highest stress. Regarding the fatigue life distribution, the simulation results differed from the experiment results by only 6.4%. Additionally, the effects of mold compound protection type and thickness on fatigue life were investigated. When the thickness was changed from 85 to 25 μ m, the solder ball fatigue life increased to approximately 1230 cycles, which satisfies the production standard of 500 cycles and is 1.86 times longer than the fatigue life in the existing production line. Reduction in mold compound thickness reduced the amount of material required to 29% of that in the current production line. The model established in this study is expected to be applied in future integrated circuit package design for product reliability.

This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death-birth technique. The effects of the cure-dependent volumetric shrinkage, geometric nonlinearity, and gravity loading on the process-induced warpage are examined. The study starts from experimental characterization of the temperature-dependent material properties of the applied liquid type epoxy molding compound (EMC) system through dynamic mechanical analysis (DMA) and thermal mechanical analysis. Furthermore, its cure state (heat of reaction and degree of cure (DOC)) during the compression molding process (CMP) is measured by differential scanning calorimetry (DSC) tests. Besides, the cure dependent-volumetric (chemical) shrinkages of the EMC system after the in-mold cure (IMC) and postmold cure (PMC) are experimentally determined by which the volumetric shrinkage at the gelation point is predicted through a linear extrapolation approach. To demonstrate the effectiveness of the proposed theoretical model, the prediction results are compared against the inline warpage measurement data. One possible cause of the asymmetric/nonaxisymmetric warpage is also addressed. Finally, the influences of some geometric dimensions on the warpage of the molded wafer are identified through parametric analysis.

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.

Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Recent advances in flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be presented in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended.

This study aims at investigating a polymer-based air-gap creation method for the packaging of microelectromechanical systems (MEMS), and exploring the chemical composition of the polymer residue on the final package. Polymer-based air-gap formation utilizes thermal decomposition of a sacrificial polymer, poly(propylene carbonate) (PPC), encapsulated within an overcoat polymer. BCB (Cyclotene 4026-46) was used as the overcoat material because decomposition products of sacrificial polymer are able to permeate through it, leaving an embedded air-gap structure around the MEMS device. Size-compatibility and cleanliness of MEMS devices are important attributes of the polymer-based air-gap MEMS packaging approach. This study provides a framework for size-compatible and clean air-gap formation by selecting the type of PPC, optimizing thermal treatment steps, identifying air-gap formation options, assessing air-gap formation performance, and analyzing the chemical composition of the residue. The air-gap formation processes using photosensitive PPC films had at least twice the residue compared to processes using nonphotosensitive PPC films. The major contribution to the residue in photosensitive PPC films was from the photoacid generator (PAG), which was used to catalyze the thermal decomposition of the PPC. BCB is compatible with PPC, and provides mechanical stability during creation of the air-gaps. The polymer-based air-gaps provide a monolithic, low-cost, integrated circuit compatible MEMS packaging option.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Board-level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSPs) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep, and time-hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared with experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.

Cold bump pull tests performed on wafer level chip scale packages using SAC105 solder bumps show an increase in the occurrence of brittle failure modes with aging temperature and time. Fast intermetallic growth at 0–1000 h can be attributed to ( Cu , Ni ) 6 Sn 5 , while the decrease in intermetallic growth rate at t > 1000 h can be attributed to diffusion processes leading to ( Cu , Ni ) 6 Sn 5 and ( Ni , Cu ) 3 Sn 4 formation and growth. Ni diffuses toward the solder bulk and saturates at 175 – 200 ° C , while Cu diffuses from the under bump metallization (UBM) toward the solder bump at 125 – 150 ° C . Interactions between Cu and Ni atoms lead to saturation of their atomic % gradients due to intermetallic formation. Sn diffusion from the solder toward the UBM occurs at 125 – 150 ° C . The activation energy for total intermetallic growth was calculated at 0.2 eV.