Abstract

In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield, Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.

1 Introduction

In 2011, Xilinx asked Taiwan Semiconductor Manufacturing Company (TSMC) to fabricate its field-programable gate array (FPGA) system-on-chip (SoC) with the 28 nm process technology. Because of the large chip size, the yield was very poor. Then, Xilinx redesigned and split the large FPGA into four smaller chiplets as shown in Fig. 2 and TSMC manufactured the chiplets at high yield (with the 28 nm process technology) and packaged them on their chip-on-wafer-on-substrate (CoWoS) technology. CoWoS is a 2.5D IC integration, which is the key structure (substrate) to let those four chiplets do vertical and mainly lateral communications. The minimum pitch of the four redistribution layers (RDLs) on the TSV-interposer is 0.4 μm, Fig. 3. On Oct. 20, 2013, Xilinx and TSMC [1] have jointly announced the production release of the Virtex-7 HT family with 28-nm process technology, what the pair claims is the industry's first chiplet design and heterogeneous integration package in production. Since then, there are a few high-volume manufacturing (HVM) products using the chiplet design and heterogeneous integration packaging technology, which will be discussed in this study. SoC will be briefly mentioned first.

Fig. 1
Chiplet design and heterogeneous integration packaging. (a) Chip partition. (b) Chip split. (c) Multiple system and heterogeneous integration with thin-film layers. (d) Multiple system and heterogeneous integration with organic interposer. (e) Multiple system and heterogeneous integration with TSV-interposer.
Fig. 1
Chiplet design and heterogeneous integration packaging. (a) Chip partition. (b) Chip split. (c) Multiple system and heterogeneous integration with thin-film layers. (d) Multiple system and heterogeneous integration with organic interposer. (e) Multiple system and heterogeneous integration with TSV-interposer.
Close modal
Fig. 2
Xilinx/TSMC's FPGA chip splitting [1]
Fig. 2
Xilinx/TSMC's FPGA chip splitting [1]
Close modal
Fig. 3
Xilinx/TSMC's 2.5D IC integration [1]
Fig. 3
Xilinx/TSMC's 2.5D IC integration [1]
Close modal

2 System-on-Chip

System-on-chip integrates ICs with different functions such as CPU (central processing unit), GPU (graphic processing unit), memory, etc. into a single chip for the system or subsystem. The most famous SoC is Apple's application processors (AP), which are simply shown in Fig. 4 for A10 through A15. The number of transistors versus years with various feature sizes (process technology) is shown in Fig. 5. It can be seen the power of Moore's law, which increases the number of transistors and functionalities with a reduction of feature size. Unfortunately, the end of Moore's law is fast approaching, and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC.

Fig. 4
Apple's application processor (AP) SoC. Reproduced with permission. © 2023 Springer Nature.
Fig. 4
Apple's application processor (AP) SoC. Reproduced with permission. © 2023 Springer Nature.
Close modal
Fig. 5
Apple's AP. Transistor versus feature size versus year.
Fig. 5
Apple's AP. Transistor versus feature size versus year.
Close modal

3 Chiplets Design and Heterogeneous Integration Packaging

According to International Business Strategies, Fig. 6 shows the advanced design cost versus feature size through 5 nm. It can be seen that it will take more than $500 × 106 to just design the 5 nm feature size. For the 5 nm process technology high manufacturing yield development, it will take another $1 × 109.

Fig. 6
Advanced design cost versus feature size. Reproduced with permission from International Business Strategies.
Fig. 6
Advanced design cost versus feature size. Reproduced with permission from International Business Strategies.
Close modal

Figure 7 shows the plots of yield (percent of good dies) per wafer versus chip size for monolithic design and two-, three-, and four-chiplet design [2]. In general, the larger the chip size, the lower the semiconductor manufacturing yield. Also, a 360 mm2 monolithic die will have a yield of 15% while a four-chiplet design (each 99 mm2) more than doubles the yield to 37%. The total die area of the four-chiplet design incurs a ∼10% area penalty (36 mm2 for a combined silicon area of 396 mm2) but the significant improvement in yield which directly translates to lower cost.

Fig. 7
Semiconductor yield versus chip size [2]
Fig. 7
Semiconductor yield versus chip size [2]
Close modal

3.1 Chip Partition.

In chip partition and heterogeneous integration (driven by cost and technology optimization), Fig. 1(a), the SoC, such as the logic and I/Os, are partitioned into functions (chiplets): logic and I/O. These chiplets can be stacked (integrated) by the front-end CoW (chip-on-wafer) or WoW (wafer-on-wafer) methods and then assembled (integrated) on the same substrate of a single package by using heterogeneous integration techniques [138]. It should be emphasized that the front-end chiplets' integration can yield a smaller package area and better electrical performance but is optional. This integration is the focus of Secs. 48.

3.2 Chip Split.

In chip split and heterogeneous integration (driven by cost and yield), Fig. 1(b), the SoC, such as logic, is split into smaller chiplets, such as logic1, logic2, and logic3. These chiplets can be stacked (integrated) by the front-end CoW or WoW methods and then assembled on the same substrate of a single package by using heterogeneous integration techniques [138]. Again, the front-end integration of chiplets is optional. This integration is the focus of Secs. 48.

3.3 Multiple System and Heterogeneous Integration.

Besides chip partition and chip split, there is another group of chiplet design and heterogeneous integration packaging, which is called multiple system and heterogeneous integration as shown in Figs. 1(c)1(e). This group of integration is driven by formfactor and performance and will be discussed in Sec. 9.

4 Advanced Micro Devices Chiplets Design and Heterogeneous Integration Packaging

4.1 UCSB/Advanced Micro Devices Future Chiplets Design and Heterogeneous Integration Packaging.

In 2017, University of California at Santa Barbara (UCSB) and advanced micro devices (AMD) published a paper on “Cost-Effective Design of Scalable High-Performance Systems Using Active and Passive Interposers” [10]. It shows AMD's future chiplets design and heterogeneous integration packaging, which will be three-dimensional (3D) IC integration as shown in Fig. 8, i.e., the chiplets are (stacked) on top of the other chiplet such as logic, so-called the active TSV-interposer.

Fig. 8
UCSB/AMD's future chiplet design and heterogeneous integration packaging [10]
Fig. 8
UCSB/AMD's future chiplet design and heterogeneous integration packaging [10]
Close modal

4.2 Advanced Micro Devices Extreme-Performance Yield Computing.

In mid-2019, AMD introduced the second-generation EPYC (extreme-performance yield computing), 7002-series, codename Rome which doubled the number of cores to sixty-four. The second-Gen EPYC is a new breed of server processors which sets a higher standard for data centers. It shows that Rome server product makes use of a 9–2–9 package (Fig. 9) for signal connectivity with four layers above the package core for signal routing. One of the signaling layers (others are similar) is shown in Fig. 10 along with the physical position of the CCD (CPU compute die), IOD (IO die), as well as main external DRAM (dynamic random-access memory) and SerDes interfaces.

Fig. 9
AMD's EPYC shipped in 2019 [8,9]
Fig. 9
AMD's EPYC shipped in 2019 [8,9]
Close modal
Fig. 10
Structure of AMD's EPYC [8,9]
Fig. 10
Structure of AMD's EPYC [8,9]
Close modal

For high-performance servers and desktop processors the I/Os are very heavy. Analog devices and bump pitches for I/Os benefit very little from leading edge technology and is very costly. One of the solutions is to partition the SoC into chiplets reserving the expensive leading-edge silicon for CPU core while leaving the I/Os and memory interfaces in n − 1 generation silicon. Because AMD committed to keeping the EPYC package size and pin-out unchanged, there needs to be a close silicon/package codesign as the number of die increases from four in the first EPYC to nine in the second Gen EPYC.

The second Gen EPYC chiplet performance versus cost is shown in Fig. 11. AMD reveal that on TSMC's 7 nm process technology the cost to manufacture a 16-core monolithic die is more than double that of a multichiplets CPU. It can be seen from Fig. 11 that: (a) the lower the core counts, the lower the saving, (b) higher core counts and performance than possible with a monolithic design, (c) lower costs at all core count/performance points in the product line, (d) cost scales down with performance by depopulating chiplets, and (e) 14 nm process technology for IOD reduces the fixed cost. AMD also optimize the cost structure and improve die yields by using much smaller chiplets. AMD used the expensive 7 nm process technology by TSMC for the core cache dies and moved the DRAM and Pie logic to a 14 nm I/O die fabricated by Global Foundries.

Fig. 11
AMD's die cost comparison: chiplet (7 nm + 12 nm) versus monolithic (7 nm) [8,9]
Fig. 11
AMD's die cost comparison: chiplet (7 nm + 12 nm) versus monolithic (7 nm) [8,9]
Close modal

4.3 Advanced Micro Devices Three-Dimensional V-Cache.

During IEEE/ISSC 2022 [3] and IEEE/ECTC 2022 [4], AMD introduced their 3D V-Cache chiplets design and heterogeneous integration packaging. Figure 12 shows schematically AMD's 3D V-Cache chiplet design and heterogeneous integration packaging. The key components of this structure are a bottom compute die, top static random-access memory (SRAM) die, and structural dies to balance the structure and provide thermal path for heat dissipation from bottom compute die to the heat sink (Fig. 13). The bottom die (81 mm2) is the “Zen 3' CPU which is fabricated by TSMC's 7 nm process technology. The top die (41 mm2) is the extended L3 die which is also fabricated by TSMC's 7 nm process technology. The bottom die with TSV is face-down with C4 (controlled collapse chip connection) bumps. The top die is also face-down, which is face-to-back Cu–Cu hybrid bonding to the bottom die, as shown in Fig. 14. Figure 15 shows the bonding process and the bonded interface, which is fabricated by TSMC' SoIC (system on integrated chips) technology. The Cu–Cu hybrid bonding minimum pitch is 9 μm.

Fig. 12
AMD's 3D V-Cache [3,4]
Fig. 12
AMD's 3D V-Cache [3,4]
Close modal
Fig. 13
AMD's 3D V-cache. Key components [3,4].
Fig. 13
AMD's 3D V-cache. Key components [3,4].
Close modal
Fig. 14
AMD's 3D V-cache. Physical organization [3,4].
Fig. 14
AMD's 3D V-cache. Physical organization [3,4].
Close modal
Fig. 15
TSMC's SoIC SRAM (face)-to-CPU (back) Cu–Cu hybrid bonding of the AMD's 3D V-cache [5]
Fig. 15
TSMC's SoIC SRAM (face)-to-CPU (back) Cu–Cu hybrid bonding of the AMD's 3D V-cache [5]
Close modal

5 Intel's Chiplets Design and Heterogeneous Integration Packaging

5.1 Intel's Foveros Technology.

Figure 16 shows Intel's Foveros technology (announced in Dec. 2018). It can be seen that the TSV interposer is with CMOS (complementary metal-oxide-semiconductor) devices (an active interposer), just like a chip, and is face-to-face thermal compression bonded with the chiplets or SoC.

Fig. 16
Intel's Foveros 3D IC integration [13]
Fig. 16
Intel's Foveros 3D IC integration [13]
Close modal

Figures 17(a) and 17(b) show another technology, announced during SEMICON West in July 2019, by Intel called omni-directional interconnect (ODI). For ODI Type 1, Fig. 17(a), the active TSV interposers (chips) are underneath the big chip such as an SoC, and are face-to-face thermal compression bonded with the SoC. For ODI Type 2, Fig. 17(b), the active TSV interposer (bridge, i.e., chip) is underneath and connecting the chiplets/SoCs. ODI Type 3 is a special case of Type 2, in which the active interposer (or the base logic chip) is connecting the SoCs/chiplets. Intel also announced the management data input/output (MDIO) for die-to-die interface, which is used to replace the current advanced interface bus (AIB). All these heterogeneous integrations on TSV interposers are for extreme high performance, and the active TSV interposers are for even higher performance [1820].

Fig. 17
(a) ODI (Type 1) and (b) ODI (Type 2) [14]
Fig. 17
(a) ODI (Type 1) and (b) ODI (Type 2) [14]
Close modal

5.2 Intel's Lakefield.

In July 2020, Intel shipped their mobile (notebook) processor “Lakefield,” which is based on their Foveros technology (TYPE-3 of ODI). The SoC is partitioned (e.g., CPU, GPU, LPDDR4, etc.) and split (e.g., the CPU is split into one big CPU and 4 smaller CPU) into chiplets as shown in Figs. 18 and 19. These chiplets are then face-to-face bonded (stacked) on an active TSV-interposer (a large 22FFL base chip) with a CoW (chip-on-wafer) process. The interconnect between the chiplets and the logic base chip is microbump (Cu pillar + SnAg solder cap) as shown in Figs. 18 and 19. The interconnect between the base chip and the package substrate is C4 bump and between the package substrate and PCB is solder ball. The final package formant is a PoP (package-on-package) (12 mm × 12 mm × 1 mm) as shown in Fig. 18. The chiplet design and heterogeneous integration packaging is in the bottom package and the upper package is housing the memories with wire bonding technology.

Fig. 18
Intel's Lakefield shipped in August 2020 [16]
Fig. 18
Intel's Lakefield shipped in August 2020 [16]
Close modal
Fig. 19
SEM images of Intel's Lakefield [17]
Fig. 19
SEM images of Intel's Lakefield [17]
Close modal

The fabrication of the chiplets is with Intel's 10 nm process technology and of the base chip is 22 nm. Since chiplets' size is smaller and not all the chips are using the 10 nm process technology, the overall yield must be higher and thus it translates to lower cost.

It should be noted that this is the very first HVM (high volume manufacturing) of 3D chiplets integration. Also, this is the very first HVM of processors for mobile products such as the notebook by 3D IC integration.

5.3 Intel's Foveros-Direct.

During Intel Architecture Day (Aug. 13, 2020), they announced a Cu–Cu hybrid bonding for their FOVEROS technology. At IEEE Hot Chip Conference (Aug. 2021), they called it FOVEROS-Direct [20] and demonstrated that with bumpless hybrid bonding the pitch can go down to 10 μm instead of 50 μm like the Lakefield as shown in Fig. 20.

Fig. 20
Intel's Foveros-Direct (Cu–Cu hybrid bonding) [20]
Fig. 20
Intel's Foveros-Direct (Cu–Cu hybrid bonding) [20]
Close modal

5.4 Intel's Ponte Vecchio.

Another of Intel's chiplet design and heterogeneous integration packaging technology is called Ponte Vecchio GPU, or the “spaceship of a GPU” [11,17], which should be the largest and most chiplets designed to date, Figs. 2125. The Ponte Vecchio GPU will be making use of several key technologies, which will power 47 different compute chiplets and 16 thermal dies based on different process nodes and architectures. While the GPU primarily makes use of Intel's 7-nm extreme ultraviolet lithography (EUV) process node for those eight RAMBO (random access bandwidth-optimized SRAM tiles), Intel will also be producing some Xe-HPC compute dies through external fabs (such as TSMC with their 5-nm note for those 16 compute tiles). To be precise (Table 1) there are: 47 chiplets consist of 16 Xe-HPCs (internal/external), 16 thermal dies, eight Rambos (internal), two Xe-Bases (internal), 11 EMIBs (internal), two Xe-Links (external), and eight HBMs (external). The maximum top-die (chiplet) size = 41 mm2; the base die size = 650 mm2; die-to-die pitch = 36 μm; and package layers = 11–2–11, package pins = 4468, and package size =  77.5 mm × 62.5 mm (Table 1). The power envelope is 600 W. A close-up of the EMIB is shown in Figs. 23 and 24.

Fig. 21
Intel's Ponte Vecchio (spaceship of GPU) [11]
Fig. 21
Intel's Ponte Vecchio (spaceship of GPU) [11]
Close modal
Fig. 22
Schematic of Intel's Ponte Vecchio [12]
Fig. 22
Schematic of Intel's Ponte Vecchio [12]
Close modal
Fig. 23
Closed-up of Intel's Ponte Vecchio [17]
Fig. 23
Closed-up of Intel's Ponte Vecchio [17]
Close modal
Fig. 24
Key components in Intel's Ponte Vecchio [17]
Fig. 24
Key components in Intel's Ponte Vecchio [17]
Close modal
Fig. 25
Thermal management of the Ponte Vecchio GPU [11]
Fig. 25
Thermal management of the Ponte Vecchio GPU [11]
Close modal
Table 1

Key components and their dimensions in Intel's Ponte Vecchio

IntegrationFoveros + EMIB
Power envelope600 W
Transistor count> 100 B
Total tiles63 (47 functional + 16 thermal tiles)
HBM count8
Package form factor77.5 × 62.5 mm (4844 mm2)
PlatformsThree platforms
IO4 × 16 90 G SERDES, 1 × 16PCle Gen5
Total Silicon3100 mm2 Si
Silicon footprint2330 mm2 Si footprint
Package layers11–2–11 (24-layer)
2.5D count11 2.5D connections
Resistance0.15 mΩ Rpath/tile
Package pins4468 pins
Package cavity186 mm2 × four cavities
IntegrationFoveros + EMIB
Power envelope600 W
Transistor count> 100 B
Total tiles63 (47 functional + 16 thermal tiles)
HBM count8
Package form factor77.5 × 62.5 mm (4844 mm2)
PlatformsThree platforms
IO4 × 16 90 G SERDES, 1 × 16PCle Gen5
Total Silicon3100 mm2 Si
Silicon footprint2330 mm2 Si footprint
Package layers11–2–11 (24-layer)
2.5D count11 2.5D connections
Resistance0.15 mΩ Rpath/tile
Package pins4468 pins
Package cavity186 mm2 × four cavities

The thermal management of a structure with 600 W of power envelope is a challenge. Intel's strategies are (Fig. 25): (a) using thick interconnect layers in the base and compute tiles act as lateral heat spreaders, (b) using high microbump density over potential hotspots to compensate for reduced thermal spreading in a thin-die stack, and (c) using high array density of power TSVs to reduce C4 bump temperature. In addition, the compute tile thickness is increased to 160 μm to improve thermal mass for turboperformance. Furthermore, there are 16 additional thermal shield dies stacked to provide a thermal solution over exposed base die area to conduct heat. Backside metallization with solder thermal interface material (TIM) is applied on all the top dies. The TIM eliminates air gaps caused by different die stack heights to reduce thermal resistance.

5.5 Intel's Roadmap.

Intel's roadmap of chiplet design and heterogeneous integration packaging in terms of interconnect density versus power efficiency is shown in Fig. 26 [12]. It can be seen that Cu–Cu hybrid bonding with < 10 μm pad pitch, >10,000/mm2 pad density, and < 0.05ρJ/bit power are their goals soon.

Fig. 26
One of Intel's roadmaps on chiplet design and heterogeneous integration packaging [12]
Fig. 26
One of Intel's roadmaps on chiplet design and heterogeneous integration packaging [12]
Close modal

6 TSMC's Chiplets Design and Heterogeneous Integration Packaging

6.1 TSMC's System on Integrated Chips.

TSMC have been working on chiplet design and heterogeneous integration packaging for a few years [2228]. At the TSMC Annual Technology Symposium (Aug. 25, 2020), TSMC announced their 3DFabric (3D fabrication) technology for mobile, high-performance computing, automotive, and IoT (internet of things) applications. The core technology of 3Dfabric is their SoIC (system on integrated chips), which was announced during the TSMC Annual Technology Symposium (May 1, 2018) in Santa Clara, CA. 3Dfabric provides chiplet heterogeneous integrations that are fully integrated from front to back end. The application-specific platform leverages TSMC's advanced wafer technology, open innovation platform design ecosystem, and 3DFabric for fast improvements and time-to-market.

Frontend 3D hybrid bonding (stacking) technology SoIC with CoW and WoW provides flexible chip-level chiplets design and integration (Fig. 27). Comparing with the conventional microbump flip chip technology, hybrid bonding SoIC has many advantages, e.g., better electrical performance, Fig. 28(a), and density, Fig. 28(b), and better thermal performance and less energy spent per bit data as shown in Fig. 29 [28].

Fig. 27
TSMC's SoIC (system on integrated chips) versus microbump flip chip [27]
Fig. 27
TSMC's SoIC (system on integrated chips) versus microbump flip chip [27]
Close modal
Fig. 28
SoIC versus flip chip: (a) Electrical performance and (b) Pad pitch and density [26]
Fig. 28
SoIC versus flip chip: (a) Electrical performance and (b) Pad pitch and density [26]
Close modal
Fig. 29
SoIC versus typical 3D IC integration: energy and thermal resistance [28]
Fig. 29
SoIC versus typical 3D IC integration: energy and thermal resistance [28]
Close modal

6.2 TSMC's CoWoS With System on Integrated Chips.

In 3D backend package integration, CoWoS' increased envelope and enriched technology content offers exceptionally high computing performance and high memory bandwidth to meet HPC needs on clouds, data center, and high-end servers as shown in Fig. 30(a). Figure 15 shows one of AMD products fabricated by TSMC's SoIC technology.

Fig. 30
Frontend stacking of chiplets with SoIC before heterogeneous integration packaging. (a) CoWoS with SoIC. (b) InFO PoP with SoIC. Reproduced with Permission from [28]. © 2019 IEEE.
Fig. 30
Frontend stacking of chiplets with SoIC before heterogeneous integration packaging. (a) CoWoS with SoIC. (b) InFO PoP with SoIC. Reproduced with Permission from [28]. © 2019 IEEE.
Close modal

6.3 TSMC's Integrated Fan-Out Package-on-Package With System on Integrated Chips.

In another 3D backend package integration, InFO (integrated fan-out) derivative technology offers memory-to-logic, logic-to-logic, PoP (package-on-package), etc. applications as shown in Fig. 30(b).

6.4 TSMC's Roadmap.

TSMC's chiplet design and heterogeneous integration packaging roadmap is shown in Fig. 31 [27]. It can be seen that CoWoS and InFO PoP are already in HVM and CoWoS with SoIC and InFO PoP with SoIC are ramping up in HVMg.

Fig. 31
TSMC's roadmaps on CoWoS with SoIC and InFO PoP with SoIC [27]
Fig. 31
TSMC's roadmaps on CoWoS with SoIC and InFO PoP with SoIC [27]
Close modal

7 Advantages and Disadvantages of Chiplets Design and Heterogeneous Integration Packaging

The key advantages of chiplet heterogeneous integrations (chip partition and chip splitting) compared with SoCs are yield improvement (lower cost) during manufacturing, time-to-market, and cost reduction during design. Figure 7 shows the plots of yield (percent of good dies) per wafer versus chip size for monolithic design and 2-, 3-, and 4-chiplet design [2]. It can be seen that the smaller the chip size the higher the semiconductor manufacturing yield. The significant improvement in yield directly translates to lower costs. Also, chip partitioning will enhance the time-to-market. Furthermore, chiplets with CPU cores can reduce silicon design and manufacturing costs. Finally, there is also thermal benefit to using chiplets as the chips are spread out across the package.

The disadvantages of chiplet heterogeneous integration are: (1) additional package area due to chip partition and chip splitting, (2) the chiplets interfaces (bridges) increase packaging costs, (3) more complexity and packaging design effort, and (4) past methodologies are less suitable for chiplets. Thus, the challenges (opportunities) for packaging technologists are to reduce the size of packages and provide high-density, high-performance, and low-cost chiplets interfaces – bridges.

8 Lateral Coummication Between Chiplets (Bridge)

In the past, lateral communications of chiplet design and heterogeneous integration packaging are by fine metal line width, spacing, and thickness (L/S/H) TSV-interposer or build-up organic package substrate. For example, Figs. 2 and 3 show the Virtex-7 HT family with TSV-interposer shipped by Xilinx in 2013. The TSV-interposer is known to have a very high cost. On the other hand, Fig. 9 shows AMD's second-generation EPYC server processors [8,9], the 7002-series, shipped in mid-2019. The EPYC is a two-dimensional (2D) IC integration technology, i.e., all the chiplets are side-by-side on a 9–2–9 build-up package substrate. The 20-layer fine metal L/S/H organic substrate is not cheap.

It should be noted that the requirement of lateral communications (RDLs) between chipets is fine-metal L/S/H and at a very small and local area of the chiplets. There is no reason to use the whole TSV-interposer or the whole organic build-up package substrate to support the lateral communication between chiplets. Therefore, the concept of using small area and a fine-metal L/S/H RDLs bridge to connect the chiplets to perform lateral communication (to reduce cost and enhance performance) for chiplet design and heterogeneous integration packaging has been proposed and is a very hot topic today. There are at least two different groups of bridge, namely, rigid bridge and flexible bridge. Only rigid bridge will be discussed in this study.

Rigid bridge consists of the RDLs and the substrate. Most rigid bridges are made with silicon substrate and the RDLs are fabricated on a silicon wafer. Some rigid bridges are even with TSVs. Today, most of the products and publications with bridges are rigid bridges. There are at least three groups of rigid bridges, namely, (a) rigid bridges embedded in build-up package substrate, Sec. 8.1, (b) rigid bridges embedded in fan-out EMC (epoxy molding compound) with RDLs, Sec. 8.2, and (c) hybrid bonding bridge, Sec. 8.3.

8.1 Intel's Embedded Multidie Interconnect Bridge.

The most famous rigid bridge is Intel's EMIB (embedded multidie interconnect bridge) [3942]. Figure 32 shows one of Intel's EMIB patents [39]. It can be seen that the EMIB die is embedded in the cavity of a build-up package substrate, which is supporting the chiplets.

Fig. 32
Intel's EMIB patent and structure [39]
Fig. 32
Intel's EMIB patent and structure [39]
Close modal

For EMIB, there are at least three important tasks, Figs. 32 and 33, namely: (a) wafer bumping of two different kinds of bumps on the chiplets wafer (but there are not bumps on the bridge); (b) embedding the bridge in the cavity of a build-up substrate and then laminating the top surface of the substrate; and (c) bonding the chiplets on the substrate with the embedded bridge.

Fig. 33
Intel's EMIB in build-up package substrate. Reproduced with Permission from [41]. © 2019 IEEE.
Fig. 33
Intel's EMIB in build-up package substrate. Reproduced with Permission from [41]. © 2019 IEEE.
Close modal

8.1.1 Solder Bumps for Embedded Multidie Interconnect Bridge.

It can be seen from Fig. 32 that there are two kinds of bumps on the chiplet, namely, the C4 (controlled collapse chip connection) bumps and the C2 (chip connection or copper-pillar with solder-cap micro) bumps. Thus, wafer bumping of the chiplets wafer poses a challenge, but Intel has already taken care of this issue.

8.1.2 Fabrication of Embedded Multidie Interconnect Bridge Substrate.

There are two major tasks in fabricating the organic package substrate with EMIB (Fig. 33). One is to make the EMIB, and the other is to make the substrate with EMIB. To make the EMIB, one must first build the RDLs (including the contact pads) on a Si-wafer. The way to make the RDLs depends on the L/S/H of the conductive wiring of the RDLs. Finally, attach the non-RDL side of the Si-wafer to a die-attach film, and then singulate the Si-wafer.

To make the substrate with an EMIB, first place the singulated EMIB with the die-attached film on top of the Cu foil in the cavity of the substrate, Fig. 33(a). It is followed by laminating a dielectric film on the whole organic package substrate and then, drilling (on the dielectric film) and Cu plating to fill the holes (vias) to make connections to the contact pads of the EMIB. Continue Cu plating to make lateral connections of the substrate as shown in Fig. 33(b). Then, it is followed by laminating another dielectric film on the whole substrate and drilling (on dielectric) and Cu plating to fill the holes and make contact pads, Fig. 33(c). (Smaller pads on a finer pitch are for C2 bumps, while larger pads on a gross pitch are for C4 bumps.) The organic package substrate with an EMIB is ready for bonding of the chips as shown in Fig. 33(d).

Today, the minimum metal L/S/H is 2 μm/2 μm/2 μm and the bridge size is from 2 mm × 2 mm to 8 mm × 8 mm [40], but most are equal and less than 5 mm × 5 mm [41]. The dielectric layer thickness is 2 μm. Usually, there are ≤ 4 RDLs. One of the challenges of the EMIB technology is to fabricate the organic build-up package substrate with cavities for the silicon bridges and then laminate (with pressure and temperature) another build-up layer on top (to meet the substrate surface flatness requirement) for chiplets (with both C2 and C4 bumps) bonding. Intel and its suppliers are working toward high-yield manufacturing of the substrate.

8.1.3 Bonding Challenges for Embedded Multidie Interconnect Bridge.

Intel published a paper at IEEE/ECTC 2021 [42] that pointed out the following bonding challenges of chiplets:

  • Die bonding process.

  • Manufacturing throughput.

  • Die warpage.

  • Interface quality.

  • Die attach film material design.

  • Die shift.

  • Via-to-die-pad overlay alignment.

  • Integrated process considerations.

8.1.4 Intel's Products with Embedded Multidie Interconnect Bridge.

Figure 34 shows Intel's processor (Kaby Lake) that combines its high-performance ×86 cores with AMD's Radeon Graphics into the same processor package using Intel's own EMIB as well as HBM (2017). Unfortunately, Intel canceled all the Kaby Lake-G products in October 2019.

Fig. 34
Intel's Kaby Lake processor with AMD's Radeon graphics as well as HBM with EMIB. Reproduced with Permission from [41]. © 2019 IEEE.
Fig. 34
Intel's Kaby Lake processor with AMD's Radeon graphics as well as HBM with EMIB. Reproduced with Permission from [41]. © 2019 IEEE.
Close modal

Figure 35 shows the Agilex FPGA (field programable gate array) module. It can be seen that the FPGA and other chips are attached on top of a build-up package substrate with EMIB with fine-metal L/S/H RDLs. The TSV interposer is not needed. Figure 24 shows the Intel spaceship of GPU (Ponte Vecchio), which has 11 EMIBs.

Fig. 35
Intel's Agilex FPGA with EMIB. Reproduced with Permission from [41]. © 2019 IEEE.
Fig. 35
Intel's Agilex FPGA with EMIB. Reproduced with Permission from [41]. © 2019 IEEE.
Close modal

8.2 IBM's Direct Bonded Heterogeneous Integration.

During IEEE/ECTC2021 and 2022, IBM presented seven papers on “Direct Bonded Heterogeneous Integration (DBHi) Si Bridge” [4350], Fig. 36. The major differences between Intel's EMIB and IBM's DBHi are as follows:

Fig. 36
  • For Intel's EMIB, there are two different (C4 and C2) bumps on the chiplets (and there are no bumps on the bridge), Figs. 32 and 35, while for IBM's DBHi, there are C4 bumps on the chiplets and C2 bumps on the bridge, Fig. 36.

  • For Intel's EMIB, the bridge is embedded in the cavity of a build-up substrate with a die-attach material and then laminated with another build-up layer on top. Therefore, the substrate fabrication is very complicated as mentioned in Sec. 8.1. For IBM's DBHi, the substrate is just a regular build-up substrate with a cavity on top as shown in Fig. 37(b).

Fig. 37
IBM's DBHi. (a) C2 bumps on the bridge while C4 bumps on the chiplet and (b) Ordinary build-up package substrate with cavity [43,45].
Fig. 37
IBM's DBHi. (a) C2 bumps on the bridge while C4 bumps on the chiplet and (b) Ordinary build-up package substrate with cavity [43,45].
Close modal

8.2.1 Solder Bumps for Direct Bonded Heterogeneous Integration.

As shown in Fig. 37(a), there are C2 bumps on the bridge. However, there are C4 bumps and Cu pads on the chiplet of the same wafer. Thus, wafer bumping poses a challenge. IBM use a double lithography process to resolve this issue [43]. The first lithography is used for making the UBM and metal pad, and the second lithography is used to make the C4 bumps by injection molded solder (IMS) method.

8.2.2 DBHi Bonding Assembly.

The bonding assembly process of DBHi is very simple, Fig. 38. First, apply the nonconductive paste (NCP) on Chip 1. Then, bond the Chip 1 and the bridge with thermal compression bonding (TCB). After bonding, the NCP becomes the underfill between Chip 1 and the bridge. Then, apply NCP on the bridge and bond Chip 2 and the bridge with TCB. Those steps are followed by placing the module (Chip 1 + bridge + Chip 2) on the organic substrate with a cavity and then going through the standard flip-chip reflow assembly process.

Fig. 38
DBHi bonding process. (a) TCB of the bridge die to Chip 1 with NCP. (b) TCB of the bridge die to Chip 2 with NCP. (c) C4 solder reflow of the Chip 1 and Chip 2 on the package with cavity and then underfill [49].
Fig. 38
DBHi bonding process. (a) TCB of the bridge die to Chip 1 with NCP. (b) TCB of the bridge die to Chip 2 with NCP. (c) C4 solder reflow of the Chip 1 and Chip 2 on the package with cavity and then underfill [49].
Close modal

The stage temperature, bonding force, and bond-head temperature versus time during bonding are shown in Fig. 39 [49]. It can be seen that: (a) the bonding stage temperature (T1) is small and kept at constant all the times, (b) the bond-head temperature consists of three stages: (i) at the first stage the temperature (T2) is larger than T1, which is used to melt and flow the NCP; (ii) at the second stage the temperature (T3 = 2 T1) is the largest, which is used to reflow the solder; and (iii) at the final stage the temperature (T4) is less than T2 and larger than T1, which is used to solidify the solder joints. The underfill under the bridge is optional. Figure 36 shows the demonstration by IBM. If the bridge is very thin, e.g., 50 μm and the C2 bump is very short, e.g., 30 μm, then the cavity of the package substrate is not needed if the C4 solder bump height is > 85μm.

Fig. 39
DBHi TCB temperature-force-time profile [49]
Fig. 39
DBHi TCB temperature-force-time profile [49]
Close modal

8.2.3 Direct Bonded Heterogeneous Integration Challenges.

The challenges in IBM's DBHi are:

  • Handling and bonding of a portion of the tiny rigid bridge on a portion of the large chiplet with very fine-pitch pads.

  • Dealing with a situation in which there is more than one rigid bridge on a chiplet.

  • Dealing with a situation in which there are more than two chiplets on a package substrate.

8.3 Bridge Embedded in Fan-Out Epoxy Molding Compound With Redistribution Layers.

Intel's and IBM's rigid bridges are either embedded in or are on an organic package substrate. There is another class of rigid bridge, which is embedded in the fan-out EMC and connected to the fan-out RDL-substrate.

8.3.1 Applied Materials' Bridge-First and Face-Up Process.

On May 12, 2020, Applied Materials obtained the U.S. patent 10,651,126 [51]. The company's design embedded the bridge in EMC by the fan-out chip (bridge) first and die face-up process (Fig. 40).

Fig. 40
Applied Materials' bridge patent with fan-out bridge-first and die face-up process (US 10,651,126) [51]
Fig. 40
Applied Materials' bridge patent with fan-out bridge-first and die face-up process (US 10,651,126) [51]
Close modal

8.3.2 Unimicron's Bridge-First and Face-Down Process.

On June 21, 2022, Unimicron obtained the U.S. patent U.S. 11,410,933 [52] in which the bridge is embedded in the fan-out EMC by the chip (bridge) first and die face-down process (Fig. 41).

Fig. 41
Unimicron's bridge patent with fan-out bridge- first and die face-down process (US 11,410,933) [52]
Fig. 41
Unimicron's bridge patent with fan-out bridge- first and die face-down process (US 11,410,933) [52]
Close modal

8.3.3 IME's Bridge-Last Process.

On May 25, 2021, IME obtained the U.S. patent U.S. 11,018,080 [53] in which For the bridge is embedded in the EMC and connected to the RDL-substrate by the chip (bridge) last or RDL-first fan-out process, (Fig. 42).

Fig. 42
IME's bridge patent with fan-out bridge-last or RDL-first process (US 11,018,080) [53]
Fig. 42
IME's bridge patent with fan-out bridge-last or RDL-first process (US 11,018,080) [53]
Close modal

8.3.4 Publications by TSMC, ASE, Amkor, SPIL, IME, and Universal Chiplet Interconnect Express.

In the past couple of years, there are many publications in rigid bridges embedded in fan-out EMC with RDLs. For examples, On Aug. 25, 2020, during TSMC's Annual Technology Symposium, the company announced its integrated fanout local silicon interconnect (InFO_ LSI) and chip-on-wafer-on-substrate local silicon interconnect (CoWoS® _LSI) (Fig. 43) [54]. During IEEE/ECTC (June 2021), there were at least four papers published regarding the application of fan-out packaging technology to embed the rigid bridge in the EMC with RDLs for the chiplets to perform lateral communications. All four of these papers discuss very similar technologies. In Ref. [55], ASE embedded the bridge in the EMC using the fan-out packaging method and called it stacked Si bridge fan-out chip-on-substrate (sFOCoS) (Fig. 44). In Ref. [56], Siliconware Precision Industries Co., Ltd. (SPIL) called its similar technology fan-out embedded bridge (FO-EB) (Fig. 45). In Ref. [57], Amkor referred to its comparable technology as S-Connect fan-out interposer (Fig. 46). In Ref. [58], IME presented its bridge and called it embedded fine interconnect (EFI) (Fig. 47). During IEEE/ECTC (June 2022), IBM published six papers [4450] in this area.

Fig. 43
(a) TSMC's InFO-LSI and (b) CoWoS-LSI [54]
Fig. 43
(a) TSMC's InFO-LSI and (b) CoWoS-LSI [54]
Close modal
Fig. 44
Fig. 45
Fig. 46
Amkor's S-Connect with Si-bridge [57]
Fig. 46
Amkor's S-Connect with Si-bridge [57]
Close modal
Fig. 47
IME's bridge with EFI [58]
Fig. 47
IME's bridge with EFI [58]
Close modal

An important consortium concerned with bridge technology is the Universal Chiplet Interconnect Express® (UCIe®), Fig. 48. According to the consortium's website, the organization addresses customer requests for a more customizable, package-level integration—combining best-in-class die-to-die interconnect and protocol connections from an interoperable, multivendor ecosystem. This new open industry standard establishes a universal interconnect at the package level. The UCIe® board of directors and leadership (promoters) include founding members ASE, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung Electronics, and TSMC, along with newly elected members, Alibaba and NVIDIA.

Fig. 48
High-speed standardized chip-to-chip interface (bridge) – Universal Chiplet Interconnect Express (UCIe)
Fig. 48
High-speed standardized chip-to-chip interface (bridge) – Universal Chiplet Interconnect Express (UCIe)
Close modal

In Ref. [59], Intel published the UCIe® 1.0 specification, which provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing. Figure 49 shows examples of standard packaging and advanced packaging with chiplet design and heterogeneous integration. It can be seen that there are three different kinds of bridges for advanced packaging: (1) bridge embedded in organic package substrate; (2) bridge embedded in Si-interposer; and (3) bridge embedded in fan-out EMC with RDLs.

Fig. 49
Universal Chiplet Interconnect Express's standard and advanced packaging with bridges [59]
Fig. 49
Universal Chiplet Interconnect Express's standard and advanced packaging with bridges [59]
Close modal

8.4 Hybrid Bonding Bridge.

Unimicron proposed the use of Cu–Cu hybrid bonding for the bridge between chiplets in chiplet design and heterogeneous integration packaging, (Fig. 50). The advantages of this structure are: (1) higher density, (2) better performance, and (3) ordinary package substrate. There are at least two options: one is with C4 bumps on the package substrate, and the other is with C4 bumps on the chiplet wafer.

Fig. 50
Hybrid bonding bridge
Fig. 50
Hybrid bonding bridge
Close modal

8.4.1 C4 Bump on Package Substrate.

Figure 51 shows the process flow of a hybrid bonding bridge with C4 bumps on the package substrate. For the bridge wafer, the processing starts off with chemical vapor deposition (CVD) to make a dielectric material such as SiO2 and then it is planarized by an optimized chemical mechanical polishing (CMP) process to make the Cu dishing. Then, the bridge wafer is diced into individual chips (still on the blue tape of the wafer) after application of a protective coating layer on the wafer surfaces to prevent any particles and contaminants that may cause interface voids during the subsequent bonding process. These steps are followed by activating the bonding surface by using plasma and hydration processes for better hydrophilicity and a higher density of a hydroxyl group on the bonding surface. To process the chiplet wafer, repeat the CVD process for the SiO2, CMP for the Cu dishing, and plasma and hydration of the activation of the bonding surface. Then, pick and place the individual bridge chip on the chiplet wafer and perform the SiO2-to-SiO2 bonding at room temperature. These steps are followed by annealing to achieve covalent bonding between oxide layers and metallic bonding between Cu–Cu contacts and the diffusion of Cu atoms. For the package substrate, the process is to stencil print the solder paste on the substrate and then reflow into C4 solder bumps. For the final assembly, the bridge + chiplets module is picked and placed on the package substrate, then the C4 bumps are reflowed.

8.4.2 C4 Bump on Chiplet Wafer.

Figure 52 shows the process flow of the hybrid bonding bridge with C4 bumps on the chiplet wafer. It can be seen that, compared with the C4 bumps for the package substrate case, the process steps for the bridge wafer and the chiplet wafer are the same up to the bridge-to-chiplet wafer bonding step. After that, the C4 bumps are fabricated by wafer bumping on the chiplet wafer. Then, the chiplet wafer is diced into individual modules (bridge + chiplets with C4 bumps). The final assembly is accomplished by picking and placing the individual module on the package substrate and reflowing the C4 solder bumps.

9 Multiple System and Heterogeneous Integration

Besides the chip partition and chip split there is another group of chiplets design and heterogeneous integration packaging called multiple system and heterogenous integration, which is driven by formfactor and performance [6062]. There are at least five different kinds of multiple systems and heterogenous integrations as shown in Fig. 53, which will be discussed briefly in Secs. 9.19.5.

Fig. 51
Hybrid bonding bridge with C4 bumps on the package substrate
Fig. 51
Hybrid bonding bridge with C4 bumps on the package substrate
Close modal
Fig. 52
Hybrid bonding bridge with C4 bumps on the chiplet wafer
Fig. 52
Hybrid bonding bridge with C4 bumps on the chiplet wafer
Close modal
Fig. 53
Multiple system and heterogeneous integration on (a) package substrate, (b) package substrate with thin-film layers, (c) package substrate with organic interposer, (d) package substrate with passive TSV interposer, and (e) package substrate with active TSV interposer [61,62].
Fig. 53
Multiple system and heterogeneous integration on (a) package substrate, (b) package substrate with thin-film layers, (c) package substrate with organic interposer, (d) package substrate with passive TSV interposer, and (e) package substrate with active TSV interposer [61,62].
Close modal

9.1 Multiple System and Heterogeneous Integration on Package Substrate (2D IC Integration).

Figure 53(a) shows a multiple system and heterogeneous integration on a package substrate (2D IC integration). It can be seen that the multiple system is supported by a high-density package substrate. An example is shown in Fig. 54, where the heterogeneous integration of three chips is supported by a fine metal L/S (2 μm/2 μm) RDL-substrate [63], Fig. 55(a) shows a TSMC's patent on AiP (antenna-in-package) [64]. Figure 55(b) shows Unimicron's patent on the heterogeneous integration of the RF chip and the baseband chip on a fan-out RDL-substrate, and the patch antenna [65].

Fig. 54
Multiple system and heterogeneous integration on package substrate [63]
Fig. 54
Multiple system and heterogeneous integration on package substrate [63]
Close modal
Fig. 55
(a) TSMC's AiP [64] and (b) Unimicron's heterogeneous integration of RF chip and baseband chip on package substrate [65]
Fig. 55
(a) TSMC's AiP [64] and (b) Unimicron's heterogeneous integration of RF chip and baseband chip on package substrate [65]
Close modal

9.2 Multiple System and Heterogeneous Integration on Package Substrate With Thin-Film Layers (2.1D IC Integration).

Figure 53(b) shows a multiple system and heterogeneous integration on a package substrate with thin-film layers [33]. An example is shown in Fig. 56, where the 2 μm/2 μm (L/S) thin-film layers are built directly on top of the build-up package substrate [66,67]. However, because of the flatness of the build-up package substrate the yield loss of manufacturing the thin-film layers is very large.

Fig. 56
Shinko's heterogeneous integration of chips on package substrate with thin-film layers [66,67]
Fig. 56
Shinko's heterogeneous integration of chips on package substrate with thin-film layers [66,67]
Close modal

A new method is shown in Figs. 57 and 58 [68], where the thin-film layers with a glass temporary carrier, Fig. 57(a), and the build-up package substrate, Fig. 57(b), are built separately, and then they are combined with either PID (photo-imageable dielectric) or ABF (Ajinomoto build-up film), Fig. 58. Vias are drilled and filled (plated) with Cu through the thin-film layers and stopped at the pad of the build-up package substrate.

Fig. 57
Unimicron's heterogeneous integration of chips on package substrate with thin-film layers: (a) Thin-film layers and (b) build-up package substrate
Fig. 57
Unimicron's heterogeneous integration of chips on package substrate with thin-film layers: (a) Thin-film layers and (b) build-up package substrate
Close modal
Fig. 58
Unimicron's heterogeneous integration of chips on package substrate with thin-film layers
Fig. 58
Unimicron's heterogeneous integration of chips on package substrate with thin-film layers
Close modal

9.3 Multiple System and Heterogeneous Integration on Package Substrate With TSV-Less Interposer (2.3D IC Integration).

Figure 53(c) shows a multiple system and heterogeneous integration on a hybrid package substrate with a TSV-less interposer (or organic interposer) [6062]. The structure consists of a multiple system on a hybrid substrate which is a combination of a build-up package substrate [or high-density interconnect (HDI)], solder joints with underfill [6973], and a fine metal L/S RDL-substrate (or organic interposer). The organic interposer of the hybrid substrate can be fabricated by the fan-out chip-first packaging process [7479] or the chip-last (or RDL-first) process [80108].

For hybrid substrate with organic interposer fabricated by fan-out chip-last packaging process [80108], the organic interposer and the build-up package substrate are fabricated separately. Then, they are combined in two different assembly processes. One is to first bond the chips on the organic interposer, underfilling and EMC (epoxy molding compound) molding, and then assemble the module (chips + organic interposer) on the build-up package substrate [80101]. For example, Fig. 59 shows Samsung's multiple system and heterogeneous integration on a package substrate with a TSV-less interposer (or organic interposer) [84,85], Fig. 60 shows ASE's [9395], and Fig. 61 shows TSMC's [8689].

Fig. 59
Samsung's multiple system and heterogeneous integration on a package substrate with RDL organic interposer [84,85]
Fig. 59
Samsung's multiple system and heterogeneous integration on a package substrate with RDL organic interposer [84,85]
Close modal
Fig. 60
ASE's multiple system and heterogeneous integration on a package substrate with RDL organic interposer [86–95]
Fig. 60
ASE's multiple system and heterogeneous integration on a package substrate with RDL organic interposer [86–95]
Close modal
Fig. 61
(a) TSMC's multiple system and heterogeneous integration on a package substrate with RDL organic interposer. (b) CoWoS-R+ [86–89].
Fig. 61
(a) TSMC's multiple system and heterogeneous integration on a package substrate with RDL organic interposer. (b) CoWoS-R+ [86–89].
Close modal

The other assembly process is first to combine the organic interposer and the build-up package substrate into a hybrid substrate through the solder joints that are enhanced with underfill [102106] or through the interconnection-layer [107,108]. Then, test the combined substrate and make sure it is a known-good hybrid substrate. Finally, bond the chips on the known-good hybrid substrate. In this case, the yield loss of the hybrid substrate especially the organic interposer is easier to control and smaller. Also, there is very little chance of losing the known-good dies. Furthermore, the logistic is simpler; after receiving the known-good hybrid substrate from the substrate houses, the OSAT (outsourced semiconductor assembly and test) houses just bond the chips/HBMs on the known-good hybrid substrate.

For examples, Fig. 62 shows the heterogeneous integration of two chips on a hybrid substrate with an organic interposer made from PID [102104], Fig. 63 shows the heterogeneous integration of two chips on a hybrid substrate with an organic interposer made from ABF [105,106], and Fig. 64 shows the heterogeneous integration of three chips on a hybrid substrate made by an interconnect-layer [107,108]. It has been found that (a) the metal lines in the organic interposer made from ABF are flatter than those from PID, and (2) the solder bumps and underfill are replaced by an interconnect-layer made by prepreg with vias filled by conductive paste. Figure 65 shows the heterogeneous integration of the EIC (electrical integrated circuits) and PIC (photonic integrated circuits) on a hybrid substrate [109].

Fig. 62
Unimicron's heterogeneous integration of two chips on a package substrate with organic interposer made by PID [102–104]
Fig. 62
Unimicron's heterogeneous integration of two chips on a package substrate with organic interposer made by PID [102–104]
Close modal
Fig. 63
Unimicron's heterogeneous integration of two chips on a package substrate with organic interposer made by ABF [105,106]
Fig. 63
Unimicron's heterogeneous integration of two chips on a package substrate with organic interposer made by ABF [105,106]
Close modal
Fig. 64
Unimicron's heterogeneous integration of three chips on a hybrid substrate [107,108]
Fig. 64
Unimicron's heterogeneous integration of three chips on a hybrid substrate [107,108]
Close modal
Fig. 65
Heterogeneous integration of EIC and PIC on a package substrate with organic interposer
Fig. 65
Heterogeneous integration of EIC and PIC on a package substrate with organic interposer
Close modal

9.4 Multiple System and Heterogeneous Integration on Package Substrate With Passive TSV-Interposer (2.5D IC Integration).

Figure 53(d) shows a multiple system and heterogeneous integration on a package substrate with a passive TSV interposer [110233]. 2.5D IC integrations use a through-silicon via (TSV)-interposer to support the SoC and memories such as the high-bandwidth memory (HBM) and then it is attached to a package substrate, Fig. 53(d). The TSV-interposer consists of TSVs and RDLs and is called passive TSV-interposer.

The first papers published on 2.5D IC integration were by Leti [110,111] at ECTC2005 and 2006. On Oct. 20, 2013, Xilinx and TSMC [1] jointly announced the production release of the Virtex-7 HT family, what the pair claims is the industry's first 2.5D IC integration in production. Since then, AMD shipped their Radeon R9 Fury X GPU [176], Nvidia shipped their Pascal 100 GPU [177], Graphcore shipped their intelligence processing unit (IPU) processor (Fig. 66) [29], Fujitsu shipped their A64FX CPU (Fig. 67) [226], etc.

Fig. 66
Graphcore's multiple system and heterogeneous integration on a package substrate with a passive TSV interposer [29]
Fig. 66
Graphcore's multiple system and heterogeneous integration on a package substrate with a passive TSV interposer [29]
Close modal
Fig. 67
Fujitsu's multiple system and heterogeneous integration on a package substrate with a passive TSV interposer [226]
Fig. 67
Fujitsu's multiple system and heterogeneous integration on a package substrate with a passive TSV interposer [226]
Close modal

9.5 Multiple System and Heterogeneous Integration on Package Substrate With Active TSV-Interposer (3D IC Integration).

Figure 53(e) shows a multiple system and heterogeneous integration on a package substrate with an active TSV interposer [10,1820, 30,31,233], which is, besides TSVs and RDLs, with CMOS devices. For example, Intel's Foveros (Figs. 1619) [1820], Leti/STMicroelectronics' INTACT (Fig. 68) [30,31], and heterogeneous integration of EIC on PIC with TSVs (Fig. 69) [62].

Fig. 68
Leti/STMicroelectronics' six chiplets on a package substrate with an active TSV interposer [30,31]
Fig. 68
Leti/STMicroelectronics' six chiplets on a package substrate with an active TSV interposer [30,31]
Close modal
Fig. 69
Multiple system and heterogeneous integration of EIC on PIC with TSV interposer (an active TSV interposer)
Fig. 69
Multiple system and heterogeneous integration of EIC on PIC with TSV interposer (an active TSV interposer)
Close modal

Figure 70 shows schematically a large-body-sized glass-based interposer for high-performance computing by George Institute of Technology (GIT) [233]. It can be seen that; (a) the glass interposer with TGVs is supporting chiplets as well as active routers and passive components, and (b) there are RDLs on the active interposer's topside and bottom-side. Also, the electrical performance (insertion loss per unit length) for different traces on glass interposer is better than that on silicon. A cross section of the sample is shown in the middle of Fig. 70. It can be seen that a 100 μm-thick die embedded in the glass cavity is connected to the chiplet (not shown) on top of the TGV-interposer with RDLs.

Fig. 70
(a) Schematic of glass-based active interposer. (b) Fabricated sample. (c) Insertion loss/mm for various traces on glass active interposers and silicon [233].
Fig. 70
(a) Schematic of glass-based active interposer. (b) Fabricated sample. (c) Insertion loss/mm for various traces on glass active interposers and silicon [233].
Close modal

10 Potential Research Topics

10.1 Interconnection Technology Between Chiplets and Bridge.

For chip partition and chip split, the interface (bridge) between chiplets is one of the most important elements in chiplet design and heterogeneous integration packaging. Currently, the most used interconnect technology between the bridge and chiplets is microbump (Cu-pillar + solder cap) as shown in Fig. 71. A potential research topic is: “what is the interconnect technology between the bridge and chiplets, so the system will achieve better performance, higher density, simpler package substrate, and lower cost?”

Fig. 71
(a) Current interconnects between bridge and chips. (b)New interconnects between bridge and chips, which will yield higher density (finer pitch), better performance, and simpler package substrate.
Fig. 71
(a) Current interconnects between bridge and chips. (b)New interconnects between bridge and chips, which will yield higher density (finer pitch), better performance, and simpler package substrate.
Close modal

10.2 Structural Design and Material Selection of Multiple System and Heterogeneous Integration With Very Large Package Substrate.

The package substrate for multiple system and heterogeneous integration packaging is getting larger and larger. For example, Fig. 72(a) shows the one (85 mm x 85 mm) by Samsung [230] and Fig. 72(b) shows the one (91 mm x 91 mm) by MediaTek [76]. Assembly issues such as warpages, stretch or open solder solders, etc. exist. Thus, optimal structural design and its material selection are of utmost importance.

Fig. 72
Multiple system and heterogeneous integration on a package substrate with a passive TSV interposer. (a) Package substrate = 85 mm × 85 mm [230]. (b) Package substrate = 91 mm × 91 mm [76].
Fig. 72
Multiple system and heterogeneous integration on a package substrate with a passive TSV interposer. (a) Package substrate = 85 mm × 85 mm [230]. (b) Package substrate = 91 mm × 91 mm [76].
Close modal

10.3 Frontend Hybrid Bonding of Chiplets Before Heterogeneous Integration Packaging.

As mentioned in Secs. 3.1 and 3.2 and Figs. 1(a) and 1(b), frontend integration of some of the chiplets (before package heterogeneous integration) can yield a smaller package size and a better performance [60]. Thus, it is a very good R&D topic. Figure 73 shows the example of Cu–Cu hybrid bonding between some chiplets before they are attached to the organic interposer or the TSV interposerk.

Fig. 73
Multiple system and heterogeneous integration on a package substrate with (a)organic interposer and (b) TSV interposer. For both cases, Cu–Cu bonding some of the chiplets before heterogenous integration packaging.
Fig. 73
Multiple system and heterogeneous integration on a package substrate with (a)organic interposer and (b) TSV interposer. For both cases, Cu–Cu bonding some of the chiplets before heterogenous integration packaging.
Close modal

11 Summary and Recommendations

Some important results and recommendations are summarized as follows:

  • SoCs with chip scaling are and will be here to stay. However only a handful of companies such as Apple, Samsung, Intel, AMD, Nvidia, Huawei, Google can afford them at finer feature size (advanced nodes). Chiplet design and heterogeneous integration packaging provide alternatives (options) to SoCs, especially for advanced nodes, which most companies cannot afford.

  • Chiplet design such as chip partition and chip split are driven by semiconductor manufacturing yield and cost. Examples such as those given by Xilinx/TSMC, AMD/TSMC, and Intel have been presented.

  • Chiplet design and heterogeneous integration packaging is no-good (the opportunity) for packaging: (a) increase package size and package complexity, (b) increase packaging efforts such as bridge design, fabrication, and assembly, and (c) increase packaging cost.

  • In general, the semiconductor cost is a few times the packaging cost, therefore, the savings that can be achieved with chiplet design and heterogeneous integration packaging are worth pursuing.

  • Interface (bridge) is the most important element of chiplets design and heterogeneous integration packaging. Bridges embedded in (a) package substrate such as those given be Intel and IBM, and (b) fan-out EMC with RDLs such as those given by Applied Materials, TSMC, Unimicron, ASE, Amkor, SPIL, and IME have been briefly presented.

  • A new interconnect between the bridge and the chiplets with hybrid bonding technology has been proposed. Its advantages are higher density (finer pitch), better performance, less process steps, simpler package substrate, and lower cost.

  • Multiple systems and heterogeneous integration such as 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration are driven by formfactor and performance. Examples such as those given by TSMC, Shinko, Samsung, ASE, Graphcore, Fujitsu, Leti, STMicroelectronics, and Unimicron have been presented.

  • One of the trends in chiplet design and heterogeneous integration packaging is to develop new interconnect method between the bridge and the chiplets such that higher performance, finer pitch, higher density, simpler package substrate, and lower cost can be achieved.

  • One of the trends in chiplet design and heterogeneous integration packaging is to optimal design and material selection of multiple system and heterogeneous integration structure with very large package substrate (∼100 mm × 100 mm).

  • One of the trends in chiplet design and heterogeneous integration packaging is to have frontend integration of some of the chiplets by Cu–Cu hybrid bonding before heterogeneous integration packaging. This will lead to smaller package size, better performance, and reduce the number of bridges.

  • In order to promote/popular the chiplet design and heterogeneous integration packaging, standards are necessary! The DARPA CHIPS and UCIe are heading in the right direction.

  • EDA (electronic design automation) tools for automating system splitting and partitioning and design are desperately needed for complex chiplet design and heterogeneous integration packaging.

Acknowledgment

The author would like to thank all the authors of their papers cited in this study for their contributions to chiplet design and heterogenous integration packaging.

Data Availability Statement

Data provided by a third party listed in Acknowledgment section.

References

1.
Xilinx and TSMC, 2013, “TSMCReach Volume Production on All 28 nm CoWoS Based All Programmable 3D IC Families,” accessed Nov. 1, 2022, http://press.xilinx.com/2013-10-20-Xilinx-and-TSMCReach-Volume-Production-on-all-28 nm-CoWoS-based-All-Programmable-3D-IC-Families
2.
Netronome,
2020
  “It’s Time for Disaggregated Silicon!,” Netronome, Cranberry Twp., PA, accessed Oct. 2022, https://www.netronome.com/blog/its-time-disaggregated-silicon/
3.
Wuu
,
J.
,
Agarwal
,
R.
,
Ciraula
,
M.
,
Dietz
,
C.
,
Johnson
,
B.
,
Johnson
,
D.
,
Schreiber
,
R.
, et al.,
2022
, “
3D V-CacheTM: The Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7 nm × 86-64 CPU
,”
Proceedings of IEEE/ISSCC
, San Francisco, CA, Feb. 20–26, pp.
1
36
.https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=202202276013534442
4.
Agarwal
,
R.
,
Cheng
,
P.
,
Shah
,
P.
,
Wilkerson
,
B.
,
Swaminathan
,
R.
,
Wuu
,
J.
, and
Mandalapu
,
C.
,
2022
, “
3D Packaging for Heterogeneous Integration
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 31–June 3, pp.
1103
1107
.10.1109/ECTC51906.2022.00178
5.
Swaminathan
,
R.
,
2022
, “
The Next Frontier: Enabling Moore's Law Using Heterogeneous Integration
,”
Chip Scale Rev.
, 26(3), pp.
11
22
.
6.
Su
,
L.
,
2021
,
AMD Accelerating—The High-Performance Computing Ecosystem
,
Keynote at Computex
,
Taipei, Taiwan
.
7.
Swaminathan
,
R.
,
2021
, “
Advanced Packaging: Enabling Moore's Law's Next Frontier Through Heterogeneous Integration
,”
Proceedings of IEEE Hot Chip Conference
, Palo Alto, CA, Aug. 22–24, pp.
1
25
.
8.
Naffziger
,
S.
,
Lepak
,
K.
,
Paraschour
,
M.
, and
Subramony
,
M.
,
2020
, “
AMD Chiplet Architecture for High-Performance Server and Desktop Products
,”
IEEE/ISSCC Proceedings
, Virtual conference, Feb. 16–20, pp.
44
45
.10.1109/ISSCC19947.2020.9063103
9.
Naffziger
,
S.
,
2020
, “
Chiplet Meets the Real World: Benefits and Limits of Chiplet Designs
,”
Symposia on VLSI Technology and Circuits
, Virtual conference, June 14–19, pp.
1
39
.
10.
Stow
,
D.
,
Xie
,
Y.
,
Siddiqua
,
T.
, and
Loh
,
G.
,
2017
, “
Cost-Effective Design of Scalable High-Performance Systems Using Active and Passive Interposers
,”
IEEE/ICCAD Proceedings
, Irvine, CA, Jan. 19–21, pp.
1
8
.10.1109/ICCAD.2017.8203849
11.
Gomes
,
W.
,
Koker
,
A.
,
Stover
,
P.
,
Ingerly
,
D.
,
Siers
,
S.
,
Venkataraman
,
S.
,
Pelto
,
C.
,
Shah
,
T.
, et al.,
2022
, “
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing
,”
Proceedings of IEEE/ISSCC
, San Francisco, CA, Feb. 20–26, pp.
42
44
.10.1109/ISSCC42614.2022.9731673
12.
Sheikh
,
F.
,
Nagisetty
,
R.
,
Karnik
,
T.
, and
Kehlet
,
D.
,
2021
, “
2.5D and 3D Heterogeneous Integration – Emerging Applications
,”
IEEE Solid-State Circuits Mag.
,
13
(
4
), pp.
77
87
.10.1109/MSSC.2021.3111386
13.
Prasad
,
C.
,
Chugh
,
S.
,
Greve
,
H.
,
Ho
,
I.
,
Kabir
,
E.
,
Lin
,
C.
,
Maksud
,
M.
, et al.,
2020
, “
Silicon Reliability Characterization of Intel's Foveros 3D Integration Technology for Logic-on-Logic Die Stacking
,”
Proceedings of IEEE International Reliability Physics Symposium
, Grapevine, TX, Apr. 28–May 3, pp.
1
5
.10.1109/IRPS45951.2020.9129277
14.
Wade
,
M.
,
Anderson
,
E.
,
Ardalan
,
S.
,
Bhargava
,
P.
,
Buchbinder
,
S.
,
L. Davenport
,
M.
,
Fini
,
J.
, et al.,
2020
, “
TeraPHY: A Chiplet Technology for LowPower, High-Bandwidth in-Package Optical I/O
,”
IEEE Comput. Soc.
,
40
(
2
), pp.
63
71
.10.1109/MM.2020.2976067
15.
Abdennadher
,
S.
,
2021
, “
Testing Inter-Chiplet Communication Interconnects in a Disaggregated SoC Design
,”
Proceedings of IEEE/DTS
, Sfax, Tunisia, June 7–10, pp.
1
7
.10.1109/DTS52014.2021.9498132
16.
Intel,
2020
, Intel Architecture Day, Intel, Santa Clara, CA.
17.
Gelsinger
,
P.
,
2021
,
Engineering the future
, Intel Unleashed Webcast,
Intel
,
Santa Clara, CA
.
18.
Ingerly
,
D.
,
Amin
,
S.
,
Aryasomayajula
,
L.
,
Balankutty
,
A.
,
Borst
,
D.
,
Chandra
,
A.
,
Cheemalapati
,
K.
, et al.,
2019
, “
Foveros: 3D Integration and the Use of Face-to-Face Chip Stacking for Logic Devices
,”
IEEE/IEDM Proceedings
, San Francisco, CA, Dec. 7–11, pp.
19.6.1
19.6.4
.10.1109/IEDM19573.2019.8993637
19.
Gomes
,
W.
,
Khushu
,
S.
,
Ingerly
,
D.
,
Stover
,
P.
,
Chowdhury
,
N.
,
O'Mahony
,
F.
,
Balankutty
,
A.
, et al.,
2020
, “
Lakefield and Mobility Computer: A 3D Stacked 10 nm and 2FFL Hybrid Processor System in 12 × 12 mm2, 1 mm Package-on-Package
,”
IEEE/ISSCC Proceedings
, Hiroshima, Japan, Nov. 9–11, pp.
40
41
.https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=202002258182242944
20.
Mahajan
,
R.
, and
Sane
,
S.
,
2021
, “
Advanced Packaging Technologies for Heterogeneous Integration
,”
Proceedings of IEEE Hot Chip Conference
, Palo Alto, CA, Aug. 22–24, pp.
1
44
.https://hc33.hotchips.org/assets/program/tutorials/Tutorial_Mahajan_Sane_HotChips_2021_Talk_final_Formatted_1.pdf
21.
WikiChip,
2020
, “
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
,” WikiChip, San Jose, CA, accessed Oct. 2021, https://en.wikichip.org/wiki/chiplet
22.
Liang
,
S.
,
Wu
,
G.
,
Yee
,
K.
,
Wang
,
C.
,
Cui
,
J.
, and
Yu
,
D.
,
2022
, “
High Performance and Energy Efficient Computing With Advanced SoICTM Scaling
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
1090
1094
.10.1109/ECTC51906.2022.00176
23.
Chiang
,
Y.
,
Tai
,
S.
,
Wu
,
W.
,
Yeh
,
J.
,
Wang
,
C.
, and
Yu
,
D.
,
2021
, “
InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
130
135
.10.1109/ECTC32696.2021.00033
24.
Huang
,
P.
,
Lu
,
C.
,
Wei
,
W.
,
Chiu
,
C.
,
Ting
,
K.
,
Hu
,
C.
,
Tsai
,
C.
, and
Hou
,
S.
,
2021
, “
Wafer Level System Integration of the Fifth Generation CoWoS®-S With High Performance Si Interposer at 2500 mm2
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
101
104
.
25.
Wu
,
J.
,
Chen
,
C.
,
Lee
,
C.
,
Liu
,
C.
, and
Yu
,
D.
,
2021
, “
SoIC- an Ultra Large Size Integrated Substrate Technology Platform for HPC Applications
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
28
33
.
26.
Chen
,
M. F.
,
Lin
,
C. S.
,
Liao
,
E. B.
,
Chiou
,
W. C.
,
Kuo
,
C. C.
,
Hu
,
C. C.
,
Tsai
,
C. H.
, et al.,
2020
, “
SoIC for Low-Temperature, Multi-Layer 3D Memory Integration
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
855
860
.10.1109/ECTC32862.2020.00139
27.
Chen
,
Y. H.
,
Yang
,
C. A.
,
Kuo
,
C. C.
,
Chen
,
M. F.
,
Tung
,
C. H.
,
Chiou
,
W. C.
, and
Yu
,
D.
,
2020
, “
Ultra High Density SoIC With Sub-Micron Bond Pitch
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
576
581
.10.1109/ECTC32862.2020.00096
28.
Chen
,
F.
,
Chen
,
M.
,
Chiou
,
W.
, and
Yu
,
D.
,
2019
, “
System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
594
599
.10.1109/ECTC.2019.00095
29.
Moore
,
S.
,
2022
, “
Graphcore Uses TSMC 3D Chip Tech to Speed AI by 40%
,”
IEEE Spectrum
, Mar. 3.https://spectrum.ieee.org/graphcore-ai-processor
30.
Coudrain
,
P.
,
Charbonnier
,
J.
,
Garnier
,
A.
,
Vivet
,
P.
,
Vélard
,
R.
,
Vinci
,
A.
,
Ponthenier
,
F.
, et al.,
2019
, “
Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures
,”
Proceedings of IEEE/ECTC
, Las Vegas, NV, May 28–31, pp.
569
578
.10.1109/ECTC.2019.00092
31.
Vivet
,
P. E.
,
Guthmuller
,
Y.
,
Thonnart
,
G.
,
Pillonnet
,
C.
,
Fuguet
,
I.
,
Miro-Panades
,
G.
,
Moritz
,
J.
, et al.,
2021
, “
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
,”
IEEE J. Solid-State Circuits
,
56
(
1
), pp.
79
97
.10.1109/JSSC.2020.3036341
32.
Lau
,
J. H.
,
2023
,
Chiplet Design and Heterogeneous Integration Packaging
,
Springer
,
New York
.
33.
Lau
,
J. H.
,
2021
,
Semiconductor Advanced Packaging
,
Springer
,
New York
.
34.
Lau
,
J. H.
,
2019
,
Heterogeneous Integrations
,
Springer
,
New York
.
35.
Lau
,
J. H.
,
2018
,
Fan-Out Wafer-Level Packaging
,
Springer
,
New York
.
36.
Lau
,
J. H.
,
2016
,
3D IC Integration and Packaging
,
McGraw-Hill
,
New York
.
37.
Lau
,
J. H.
,
2013
,
Through-Silicon Via (TSV) for 3D Integration
,
McGraw-Hill
,
New York
.
38.
Lau
,
J. H.
,
2011
,
Reliability of RoHS Compliant 2D & 3D IC Interconnects
,
McGraw-Hill
,
New York
.
39.
Chiu
,
C.
,
Qian
,
Z.
, and
Manusharow
,
M.
, “
2014
, “
Bridge Interconnect With Air Gap in Package Assembly
,” U.S. Patent No.
8,872,349
.https://patents.google.com/patent/US20140070380A1/en
40.
Mahajan
,
R.
,
Sankman
,
R.
,
Patel
,
N.
,
Kim
,
D.
,
Aygun
,
K.
,
Qian
,
Z.
,
Mekonnen
,
Y.
, et al.,
2016
, “
Embedded Multi-Die Interconnect Bridge (EMIB) – A High-Density, High-Bandwidth Packaging Interconnect
,”
Proceedings of IEEE/ECTC
, Las Vegas, NV, May 31–June 3, pp.
557
565
.10.1109/ECTC.2016.201
41.
Mahajan
,
R.
,
Qian
,
Z.
,
Viswanath
,
R. S.
,
Srinivasan
,
S.
,
Aygun
,
K.
,
Jen
,
W.-L.
,
Sharan
,
S.
, and
Dhall
,
A.
,
2019
, “
Embedded Multidie Interconnect Bridge - A Localized, High-Density Multichip Packaging Interconnect
,”
IEEE Trans. Compon., Packaging Manuf. Technol.
,
9
(
10
), pp.
1952
1962
.10.1109/TCPMT.2019.2942708
42.
Duan
,
G.
,
Knaoka
,
Y.
, and
McRee
,
R.
,
2021
, “
Die Embedded Challenges for EMIB Advanced Packaging Technology
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1
7
.10.1109/ECTC32696.2021.00012
43.
Sikka
,
K.
,
Bonam
,
R.
,
Liu
,
Y.
,
Andry
,
P.
,
Parekh
,
D.
,
Jain
,
A.
,
Bergendahl
,
M.
, et al.,
2021
, “
Direct Bonded Heterogeneous Integration (DBHi) Si Bridge
,”
IEEE/ECTC Proceedings
, Virtual conference, June 1–4, pp.
136
147
.10.1109/ECTC32696.2021.00034
44.
Matsumoto
,
K.
,
Bergendahl
,
M.
,
Sikka
,
K.
,
Kohara
,
S.
,
Mori
,
H.
, and
Hisada
,
T.
,
2021
, “
Thermal Analysis of DBHi (Direct Bonded Heterogeneous Integration) Si Bridge
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1382
1390
.10.1109/ECTC32696.2021.00222
45.
Jain
,
A.
,
Sikka
,
K.
,
Gomez
,
J.
,
Parekh
,
D.
,
Bergendahl
,
M.
,
Borkulo
,
J.
,
Biesheuvel
,
K.
,
Doll
,
R.
, and
Mueller
,
M.
,
2021
, “
Laser vs. Blade Dicing for Direct Bonded Heterogeneous Integration (DBHi) Si Bridge
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1125
1130
.10.1109/ECTC32696.2021.00184
46.
Marushima
,
C.
,
Aoki
,
T.
,
Nakamura
,
K.
,
Miyazawa
,
R.
,
Horibe
,
A.
,
Sousa
,
I.
,
Sikka
,
K.
, and
Hisada
,
T.
,
2022
, “
Dimensional Parameters Controlling Capillary Underfill Flow for Void-Free Encapsulation of a Direct Bonded Heterogeneous Integration (DBHi) Si-Bridge Package
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
586
590
.10.1109/ECTC51906.2022.00098
47.
Horibe
,
A.
,
Watanabe
,
T.
,
Marushima
,
C.
,
Mori
,
H.
,
Kohara
,
S.
,
Yu
,
R.
,
Bergendahl
,
M.
, et al.,
2022
, “
Characterization of Non-Conductive Paste Materials (NCP) for Thermocompression Bonding in a Direct Bonded Heterogeneously Integrated (DBHi) Si-Bridge Package
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
625
630
.10.1109/ECTC51906.2022.00105
48.
Horbe
,
A.
,
Marushima
,
C.
,
Watanabe
,
T.
,
Jian
,
A.
,
Turcotte
,
E.
,
Sousa
,
I.
,
Sikka
,
K.
, and
Hisada
,
T.
,
2022
, “
Super Fine Jet Underfill Dispense Technique for Robust Micro Joint in Direct Bonded Heterogeneous Integration (DBHi) Silicon Bridge Packages
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
631
634
.10.1109/ECTC51906.2022.00106
49.
Chowehury
,
P.
,
Sakuma
,
K.
,
Raghawan
,
S.
,
Bergendahl
,
M.
,
Sikka
,
K.
,
Kohara
,
S.
,
Hisada
,
T.
,
Mori
,
H.
,
Taneja
,
D.
, and
Sousa
,
I.
,
2022
, “
Thermo-Mechanical Analysis of Thermal Compression Bonding Chip-Joint Process
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
579
585
.https://research.ibm.com/publications/thermomechanical-analysis-of-thermal-compression-bonding-chip-join-process
50.
Qiu
,
Y.
,
Beilliard
,
Y.
,
Sousa
,
I.
, and
Drouin
,
D.
,
2022
, “
A Self-Aligned Structure Based on V-Groove for Accurate Silicon Bridge Placement
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
668
673
.10.1109/ECTC51906.2022.00112
52.
Lau
,
J. H.
,
Ko
,
C.
,
Lin
,
P.
,
Tseng
,
T.
,
Tain
,
R.
, and
Yang
,
H.
,
2022
, “
Package Structure and Manufacturing Method Thereof
,” U.S. Patent No.
11,410,933
.https://patents.google.com/patent/US7989937
53.
Weerasekera
,
R.
,
Bhattacharys
,
S.
,
Chang
,
K.
, and
Rao
,
V.
, “
2021
, “
Semiconductor Package and Method of Forming the Same
,” U.S. Patent No. 11,018,080.
54.
TSMC,
2020
, “TSMC,”
TSMC's Annual Technology Symposium
, Taipei, Taiwan, Aug. 25.
55.
Cao
,
L.
,
Lee
,
T.
,
Chang
,
Y.
,
Huang
,
S.
,
On
,
J.
,
Lin
,
E.
, and
Yang
,
O.
,
2021
, “
Advanced HDFO Packaging Solutions for Chiplets Integration in HPC Application
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
8
13
.10.1109/ECTC32696.2021.00013
56.
You
,
O. J.
,
Li
,
J.
,
Ho
,
D.
,
Li
,
J.
,
Zhuang
,
M.
,
Lai
,
D.
,
Chung
,
C.
, and
Wang
,
Y.
,
2021
, “
Electrical Performances of Fan-Out Embedded Bridge
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
2030
2034
.10.1109/ECTC32696.2021.00320
57.
Lee
,
J.
,
Yong
,
G.
,
Jeong
,
M.
,
Jeon
,
J.
,
Han
,
D.
,
Lee
,
M.
,
Do
,
W.
,
Sohn
,
E.
,
Kelly
,
M.
,
Hiner
,
D.
, and
Khim
,
J.
,
2021
, “
S-Connect Fan-Out Interposer for Next-Gen Heterogeneous Integration
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
96
100
.10.1109/ECTC32696.2021.00027
58.
Chong
,
C.
,
Lim
,
T.
,
Ho
,
D.
,
Yong
,
H.
,
Choong
,
C.
,
Lim
,
S.
, and
Bhattacharya
,
S.
,
2021
, “
Heterogeneous Integration With Embedded Fine Interconnect
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
2216
2221
.10.1109/ECTC32696.2021.00348
59.
Sharma
,
D.
,
Pasdast
,
G.
,
Qian
,
Z.
, and
Ayg Un
,
K.
,
2022
, “
Universal Chiplet Interconnect Express (UCIe®): an Open Industry Standard for Innovations With Chiplets at Package Level
,”
IEEE Trans. CPMT
,
12
(
9
), pp.
1423
1431
.10.1109/TCPMT.2022.3207195
60.
Lau
,
J. H.
,
2022
, “
Recent Advances and Trends in Advanced Packaging
,”
IEEE Trans. CPMT
,
12
(
2
), pp.
228
252
.10.1109/TCPMT.2022.3144461
61.
Lau
,
J. H.
,
2022
, “
Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV-Less Interposers
,”
IEEE Trans. CPMT
,
12
(
8
), pp.
1271
1281
.10.1109/TCPMT.2022.3194374
62.
Lau
,
J. H.
,
2023
, “
Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV-Interposers
,”
IEEE Trans. CPMT
,
13
(
1
), pp.
3
25
.10.1109/TCPMT.2023.3234007
63.
Lau
,
J. H.
,
Ko
,
C.
,
Yang
,
K.
,
Peng
,
C.
,
Xia
,
T.
,
Lin
,
P.
,
Chen
,
J.
, et al.,
2020
, “
Panel-Level Fan-Out RDL-First Packaging for Heterogeneous Integration
,”
IEEE Trans. CPMT
,
10
(
7
), pp.
1125
1137
.10.1109/TCPMT.2020.2996658
64.
Chuang
,
N.
,
Yang
,
C.
, and
Wu
,
K.
, “
2019
, “
Integrated Fan-Out Package Having Multi-Band Antenna and Method of Forming the Same
,” U.S. Patent No.
10,312,112
.https://patents.google.com/patent/US20160104940
65.
Lau
,
J. H.
,
Shen
,
Y.
,
Tseng
,
T.
,
Cheng
,
C.
, and
Wang
,
P.
,
2021
, “
Chip Package Structure Having At Least One Chip and At Least One Thermal Conductive Element and Manufacturing Method Thereof
,” U.S. Patent No. 11,145,610.
66.
Shimizu
,
N.
,
Kaneda
,
W.
,
Arisaka
,
H.
,
Koizumi
,
N.
,
Sunohara
,
S.
,
Rokugawa
,
A.
, and
Koyama
,
T.
,
2013
, “
Development of Organic Multi Chip Package for High Performance Application
,”
IMAPS Proc. Int. Symp. Microelectron.
,
2013
(
1
), p. 414.10.4071/isom-2013-TP65
67.
Oi
,
K.
,
Otake
,
S.
,
Shimizu
,
N.
,
Watanabe
,
S.
,
Kunimoto
,
Y.
,
Kurihara
,
T.
,
Koyama
,
T.
,
Tanaka
,
M.
, et al.,
2014
, “
Development of New 2.5D Package With Novel Integrated Organic Interposer Substrate With Ultra-Fine Wiring and High Density Bumps
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 27–30, pp.
348
353
.10.1109/ECTC.2014.6897310
68.
Lau
,
J. H.
,
Tain
,
R.
,
Ko
,
C.
, and
Tseng
,
T.
,
2022
, “
Hybrid Substrate for High-Density Applications
,” U.S. Patent.
69.
Lau
,
J. H.
, and
Lee
,
N. C.
,
2020
,
Assembly and Reliability of Lead-Free Solder Joints
,
Springer
,
New York
.
70.
Lau
,
J. H.
, and
Pao
,
Y.
,
1997
,
Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies
,
McGraw-Hill
,
New York
.
71.
Lau
,
J. H.
,
1991
,
Solder Joint Reliability: Theory and Applications
,
Van Nostrand Reinhold
,
New York
.
72.
Lau
,
J. H.
,
2021
, “
State of the Art of Lead-Free Solder Joint Reliability
,”
ASME Trans., J. Electron. Packaging
,
143
(
2
), p.
020803
.10.1115/1.4048037
73.
Lau
,
J. H.
,
Zhang
,
Q.
,
Li
,
M.
,
Yeung
,
K.
,
Cheung
,
Y.
,
Fan
,
N.
,
Wong
,
Y.
,
Zahn
,
M.
, and
Koh
,
M.
,
2015
, “
Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates
,”
IEEE Trans. CPMT
,
5
(
7
), pp.
1027
1035
.10.1109/TCPMT.2015.2443841
74.
Yoon
,
S.
,
Tang
,
P.
,
Emigh
,
R.
,
Lin
,
Y.
,
Marimuthu
,
P.
, and
Pendse
,
R.
,
2013
, “
Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1855
1860
.10.1109/ECTC.2013.6575830
75.
Chen
,
N. C.
,
Hsieh
,
T.
,
Jinn
,
J.
,
Chang
,
P.
,
Huang
,
F.
,
Xiao
,
J.
,
Chou
,
A.
, and
Lin
,
B.
,
2016
, “
A Novel System in Package With Fan-Out WLP for High Speed SERDES Application
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 31–June 3, pp.
1496
1501
.10.1109/ECTC.2016.43
76.
Yip
,
L.
,
Lin
,
R.
,
Lai
,
C.
, and
Peng
,
C.
,
2022
, “
Reliability Challenges of High-Density Fan-Out Packaging for High-Performance Computing Applications
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 31–June 3, pp.
1454
1458
.10.1109/ECTC51906.2022.00232
77.
Lin
,
Y.
,
Lai
,
W.
,
Kao
,
C.
,
Lou
,
J.
,
Yang
,
P.
,
Wang
,
C.
, and
Hseih
,
C.
,
2016
, “
Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 31–June 3, pp.
13
18
.10.1109/ECTC.2016.267
78.
Yu
,
D.
,
2018
, “
Advanced System Integration Technology Trends
,”
SiP Global Summit
,
SEMICON
Taiwan
, Sept. 6.
79.
Kurita
,
Y.
,
Kimura
,
T.
,
Shibuya
,
K.
,
Kobayashi
,
H.
,
Kawashiro
,
F.
,
Motohashi
,
N.
, and
Kawano
,
M.
,
2010
, “
Fan-Out Wafer Level Packaging With Highly Flexible Design Capabilities
,”
IEEE/ESTC Proceedings
, Berlin, Germany, Sept. 13–16, pp.
1
6
.10.1109/ESTC.2010.5642888
80.
Motohashi
,
N.
,
Kimura
,
T.
,
Mineo
,
K.
,
Yamada
,
Y.
,
Nishiyama
,
T.
,
Shibuya
,
K.
,
Kobayashi
,
H.
,
Krita
,
Y.
, and
Kawano
,
M.
,
2011
, “
System in a Wafer-Level Package Technology With RDL-First Process
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 31–June 3, pp.
59
64
.10.1109/ECTC.2011.5898492
81.
Huemoeller
,
R.
, and
Zwenger
,
C.
,
2015
, “
Silicon Wafer Integrated Fan-Out Technology
,”
Chip Scale Rev.
, 19(2), pp.
34
37
.https://c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2018/01/04_15-Silicon_Wafer_Integrated_Fan-out_Technology.pdf
82.
Lim
,
H.
,
Yang
,
J.
, and
Fuentes
,
R.
,
2018
, “
Practical Design Method to Reduce Crosstalk for Silicon Wafer Integration Fan-Out Technology (SWIFT) Packages
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
2205
2211
.10.1109/ECTC.2018.00332
83.
Jayaraman
,
S.
,
2022
, “
Advanced Packaging: HDFO for Next Generation Devices
,”
Proceedings of IWLPC
, San Jose, CA, Feb. 15–17, pp.
1
28
.
84.
Suk
,
K.
,
Lee
,
S.
,
Kim
,
J.
,
Lee
,
S.
,
Kim
,
H.
,
Lee
,
S.
,
Kim
,
P.
,
Kim
,
D.
,
Oh
,
D.
, and
Byun
,
J.
,
2018
, “
Low-Cost Si-Less RDL Interposer Package for High Performance Computing Applications
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
64
69
.10.1109/ECTC.2018.00018
85.
You
,
S.
,
Jeon
,
S.
,
Oh
,
D.
,
Kim
,
K.
,
Kim
,
J.
,
Cha
,
S.
, and
Kim
,
G.
,
2018
, “
Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1295
1301
.10.1109/ECTC.2018.00199
86.
Lin
,
Y.
,
Yew
,
M.
,
Liu
,
M.
,
Chen
,
S.
,
Lai
,
T.
,
Kavle
,
P.
,
Lin
,
C.
, et al.,
2019
, “
Multilayer RDL Interposer for Heterogeneous Device and Module Integration
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
931
936
.10.1109/ECTC.2019.00145
87.
Lin
,
P.
,
Yew
,
M.
,
Yeh
,
S.
,
Chen
,
S.
,
Lin
,
C.
,
Chen
,
C.
,
Hsieh
,
C.
, et al.,
2021
, “
Reliability Performance of Advanced Organic Interposer (CoWoS-R) Packages
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
723
728
.10.1109/ECTC32696.2021.00125
88.
Lin
,
M.
,
Liu
,
M.
,
Chen
,
H.
,
Chen
,
S.
,
Yew
,
M.
,
Chen
,
C.
, and
Jeng
,
S.
,
2022
, “
Organic Interposer CoWoS-R (Plus) Technology
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
1
6
.10.1109/ECTC51906.2022.00008
89.
Jeng
,
S.-P.
, and
Liu
,
M.
,
2022
, “
Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)
,”
Proceedings of IEEE/IEDM
, San Francisco, CA, Dec. 3–7, pp.
3.2.1
3.2.4
.10.1109/IEDM45625.2022.10019517
90.
Chang
,
K.
,
Huang
,
C.
,
Kuo
,
H.
,
Jhong
,
M.
,
Hsieh
,
T.
,
Hung
,
M.
, and
Wang
,
C.
,
2019
, “
Ultra High-Density IO Fan-Out Design Optimization With Signal Integrity and Power Integrity
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
41
46
.10.1109/ECTC.2019.00014
91.
Lai
,
W.
,
Yang
,
P.
,
Hu
,
I.
,
Liao
,
T.
,
Chen
,
K.
,
Tarng
,
D.
, and
Hung
,
C.
,
2020
, “
A Comparative Study of 2.5D and Fan-Out Chip on Substrate: Chip First and Chip Last
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
354
360
.10.1109/ECTC32862.2020.00064
92.
Fang
,
J.
,
Huang
,
M.
,
Tu
,
H.
,
Lu
,
W.
, and
Yang
,
P.
,
2020
, “
A Production-Worthy Fan-Out Solution – ASE FOCoS Chip Last
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
290
295
.10.1109/ECTC32862.2020.00055
93.
Cao
,
L.
,
2022
, “
Advanced FOCOS (Fanout Chip on Substrate) Technology for Chiplets Heterogeneous Integration
,”
Proceedings of IWLPC
, San Jose, CA, Feb. 15–17, pp.
1
6
.
94.
Cao
,
L.
,
Lee
,
T.
,
Chen
,
R.
,
Chang
,
Y.
,
Lu
,
H.
,
Chao
,
N.
,
Huang
,
Y.
,
Wang
,
C.
,
Huang
,
C.
,
Kuo
,
H.
,
Wu
,
Y.
, and
Cheng
,
H.
,
2022
, “
Advanced Fanout Packaging Technology for Hybrid Substrate Integration
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
1362
1370
.10.1109/ECTC51906.2022.00219
95.
Cao
,
L.
,
2022
, “
Advanced Packaging Technology Platforms for Chiplets and Heterogeneous Integration
,”
Proceedings of IEEE/IEDM
,
San Francisco, CA
, Dec. 3–7, pp.
3.3.1
3.3.4
.10.1109/IEDM45625.2022.10019534
96.
Lee
,
T.
,
Yang
,
S.
,
Wu
,
H.
, and
Lin
,
Y.
,
2022
, “
Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
1970
1974
.10.1109/ECTC51906.2022.00309
97.
Yin
,
W.
,
Lai
,
W.
,
Lu
,
Y.
,
Chen
,
K.
,
Huang
,
H.
,
Chen
,
T.
,
Kao
,
C.
, and
Hung
,
C.
,
2022
, “
Mechanical and Thermal Characterization Analysis of Chip-Last Fan-Out Chip on Substrate
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
1711
1719
.10.1109/ECTC51906.2022.00269
98.
Li
,
J.
,
Tsai
,
F.
,
Li
,
J.
,
Pan
,
G.
,
Chan
,
M.
,
Zheng
,
L.
,
Chen
,
S.
, et al.,
2021
, “
Large Size Multilayered Fan-Out RDL Packaging for Heterogeneous Integration
,”
IEEE/EPTC Proceedings
, Virtual conference, June 1–4, pp.
239
243
.10.1109/EPTC53413.2021.9663974
99.
Miki
,
S.
,
Taneda
,
H.
,
Kobayashi
,
N.
,
Oi
,
K.
,
Nagai
,
K.
, and
Koyama
,
T.
,
2019
, “
Development of 2.3D High Density Organic Package Using Low Temperature Bonding Process With Sn-Bi Solder
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1599
1604
.10.1109/ECTC.2019.00246
100.
Murayama
,
K.
,
Miki
,
S.
,
Sugahara
,
H.
, and
Oi
,
K.
,
2020
, “
Electro-Migration Evaluation Between Organic Interposer and Build-Up Substrate on 2.3D Organic Package
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
716
722
.10.1109/ECTC32862.2020.00118
101.
Kim
,
J.
,
Choi
,
J.
,
Kim
,
S.
,
Choi
,
J.
,
Park
,
Y.
,
Kim
,
G.
,
Kim
,
S.
, et al.,
2021
, “
Cost Effective 2.3D Packaging Solution by Using Fanout Panel Level RDL
,”
IEEE/ECTC Proceedings
, Virtual conference, June 1–4, pp.
310
314
.10.1109/ECTC32696.2021.00059
102.
Lau
,
J. H.
,
Chen
,
G.
,
Chou
,
R.
,
Yang
,
C.
, and
Tseng
,
T.
,
2021
, “
Fan-Out (RDL-First) Panel-Level Hybrid Substrate for Heterogeneous Integration
,”
IEEE/ECTC Proceedings
, Virtual conference, June 1–4, pp.
148
156
.10.1109/ECTC32696.2021.00035
103.
Lau
,
J. H.
,
Chen
,
G. C.-F.
,
Huang
,
J. Y.-C.
,
Chou
,
R. T.-S.
,
Yang
,
C. C.-L.
,
Liu
,
H.-N.
, and
Tseng
,
T.-J.
,
2021
, “
Hybrid Substrate by Fan-Out RDL-First Panel-Level Packaging
,”
IEEE Trans. CPMT
,
11
(
8
), pp.
1301
1309
.10.1109/TCPMT.2021.3096786
104.
Chou
,
R.
,
Lau
,
J. H.
,
Chen
,
G.
,
Huang
,
J.
,
Yang
,
C.
,
Liu
,
N.
, and
Tseng
,
T.
,
2022
, “
Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill
,”
IMAPS Trans., J. Microelectron. Electron. Packaging
,
19
(
1
), pp.
8
17
.10.4071/imaps.1546248
105.
Chen
,
G.
,
Lau
,
J. H.
,
Chou
,
R.
,
Yang
,
C.
,
Huang
,
J.
,
Liu
,
N.
, and
Tseng
,
T.
,
2022
, “
2.3D Hybrid Substrate With Ajinomoto Build-Up Film for Heterogeneous Integration
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
30
37
.10.1109/ECTC51906.2022.00013
106.
Lau
,
J. H.
,
Chen
,
G.
,
Yang
,
C.
,
Peng
,
A.
,
Huang
,
J.
,
Ko
,
C.
,
Yang
,
H.
,
Chen
,
Y.
, and
Tseng
,
T.
,
2022
, “
Hybrid Substrates for Chiplet Design and Heterogeneous Integration Packaging
,”
Proceedings of IEEE/IEDM
,
San Francisco, CA
, Dec. 3–7, pp.
3.5.1
3.5.4
.10.1109/IEDM45625.2022.10019568
107.
Peng
,
P.
,
Lau
,
J. H.
,
Ko
,
C.
,
Lee
,
P.
,
Lin
,
E.
,
Yang
,
K.
,
Lin
,
P.
, et al.,
2021
, “
Development of High-Density Hybrid Substrate for Heterogeneous Integration
,”
IEEE CPMT Symposium Japan
, Kyoto University, Japan, Nov. 10–12, pp.
5
8
.10.1109/ICSJ52620.2021.9648860
108.
Peng
,
T. C.-Y.
,
Lau
,
J. H.
,
Ko
,
C.-T.
,
Lee
,
P.
,
Lin
,
E.
,
Yang
,
K.-M.
,
Lin
,
B. P.
, et al.,
2022
, “
High-Density Hybrid Substrate for Heterogeneous Integration
,”
IEEE Trans. CPMT
,
12
(
3
), pp.
469
478
.10.1109/TCPMT.2022.3151848
109.
Lau
,
J. H.
, and
Tseng
,
T.
,
2022
, “
Package Structure and Optical Signal Transmitter
,” U.S. Patent.
110.
Souriau
,
J.
,
Lignier
,
O.
,
Charrier
,
M.
, and
Poupon
,
G.
,
2005
, “
Wafer Level Processing of 3D System in Package for RF and Data Applications
,”
IEEE/ECTC Proceedings
, Buena Vista, FL, May 31–June 3, pp.
356
361
.10.1109/ECTC.2005.1441291
111.
Henry
,
D.
,
Belhachemi
,
D.
,
Souriau
,
J.-C.
,
Brunet-Manquat
,
C.
,
Puget
,
C.
,
Ponthenier
,
G.
,
Vallejo
,
J.
, et al.,
2006
, “
Low Electrical Resistance Silicon Through Vias: Technology and Characterization
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 30–June 2, pp.
1360
1366
.10.1109/ECTC.2006.1645834
112.
Lau
,
J. H.
, and
Tang
,
G.
,
2009
, “
Thermal Management of 3D IC Integration With TSV (Through Silicon Via)
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 26–29, pp.
635
640
.10.1109/ECTC.2009.5074080
113.
Selvanayagam
,
C.
,
Lau
,
J. H.
,
Zhang
,
X.
,
Seah
,
S.
,
Vaidyanathan
,
K.
, and
Chai
,
T.
,
2009
, “
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
,”
IEEE Trans. Adv. Packaging
,
32
(
4
), pp.
720
728
.10.1109/TADVP.2009.2021661
114.
Khan
,
N.
,
Yu
,
L.
,
Tan
,
P.
,
Ho
,
S.
,
Su
,
N.
,
Wai
,
H.
,
Vaidyanathan
,
K.
,
Pinjala
,
D.
,
Lau
,
J. H.
, and
Chuan
,
T.
,
2009
, “
3D Packaging With Through Silicon Via (TSV) for Electrical and Fluidic Interconnections
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 26–29, pp.
1153
1158
.10.1109/ECTC.2009.5074157
115.
Yu
,
A.
,
Khan
,
N.
,
Archit
,
G.
,
Pinjala
,
D.
,
Toh
,
K.
,
Kripesh
,
V.
,
Yoon
,
S.
, and
Lau
,
J. H.
,
2009
, “
Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages
,”
IEEE Trans. CPMT
,
32
(
3
), pp.
566
571
.10.1109/TCAPT.2009.2012719
116.
Zhang
,
X.
,
Chai
,
T.
,
Lau
,
J. H.
,
Selvanayagam
,
C.
,
Biswas
,
K.
,
Liu
,
S.
, and
Pinjala
,
D.
, et al.,
2009
, “
Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21 × 21mm) Fine-Pitch Cu/Low-k FCBGA Package
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 26–29, pp.
305
312
.10.1109/ECTC.2009.5074032
117.
Lau
,
J. H.
,
2010
, “
TSV Manufacturing Yield and Hidden Costs for 3D IC Integration
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, June 1–4, pp.
1031
1041
.10.1109/ECTC.2010.5490828
118.
Lau
,
J. H.
,
2010
, “
Design and Process of 3D MEMS Packaging
,”
IMAPS Trans., J. Microelectron. Electron. Packaging
,
7
(
1
), pp.
10
15
.10.4071/1551-4897-7.1.10
119.
Lau
,
J. H.
,
Lee
,
R.
,
Yuen
,
M.
, and
Chan
,
P.
,
2010
, “
3D LED and IC Wafer Level Packaging
,”
J. Microelectron. Int.
,
27
(
2
), pp.
98
105
.10.1108/13565361011034786
120.
Lau
,
J. H.
,
Chan
,
Y. S.
, and
Lee
,
S. W. R.
, “
Thermal-Enhanced and Cost-Effective 3D IC Integration With TSV Interposers for High-Performance Applications
,”
ASME
Paper No. IMECE2010-40975. 10.1115/IMECE2010-40975
121.
Tang
,
G. Y.
,
Tan
,
S.
,
Khan
,
N.
,
Pinjala
,
D.
,
Lau
,
J. H.
,
Yu
,
A.
,
Kripesh
,
V.
, and
Toh
,
K.
,
2010
, “
Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules
,”
IEEE Trans. CPMT
,
33
(
1
), pp.
184
195
.10.1109/TCAPT.2009.2033039
122.
Khan
,
N.
,
Rao
,
V.
,
Lim
,
S.
,
We
,
H.
,
Lee
,
V.
,
Zhang
,
X.
,
Liao
,
E.
, et al.,
2010
, “
Development of 3-D Silicon Module With TSV for System in Packaging
,”
IEEE Trans. CPMT
,
33
(
1
), pp.
3
9
.10.1109/TCAPT.2009.2037608
123.
Lau
,
J. H.
,
Lee
,
S.
,
Yuen
,
M.
,
Wu
,
J.
,
Lo
,
C.
, “
Fan
,
H.
, and
Chen
,
H.
,
2013
, “
Apparatus Having Thermal-Enhanced and Cost-Effective 3D IC Integration Structure With Through Silicon Via Interposer
,” U.S. Patent No.
8,604,603
.https://patents.google.com/patent/US20100213600
124.
Lau
,
J. H.
, “
State-of-the-Art and Trends in Through-Silicon Via (TSV) and 3D Integrations
,”
ASME
Paper No. IMECE2010-37783. 10.1115/IMECE2010-37783
125.
Lau
,
J. H.
,
Zhang
,
M. S.
, and
Lee
,
S. W. R.
,
2011
, “
Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates
,”
ASME Trans., J. Electron. Packaging
,
133
(
3
), pp.
1
7
.10.1115/1.4004861
126.
Yu
,
A.
,
Lau
,
J. H.
,
Ho
,
S.
,
Kumar
,
A.
,
Hnin
,
W.
,
Lee
,
W.
,
Jong
,
M.
, et al.,
2011
, “
Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects
,”
IEEE Trans. CPMT
,
1
(
9
), pp.
1336
1344
.10.1109/TCPMT.2011.2155655
127.
Chien
,
J.
,
Chao
,
Y.
,
Lau
,
J. H.
,
Dai
,
M.
,
Tain
,
R.
,
Dai
,
M.
,
Tzeng
,
P.
, et al.,
2011
, “
A Thermal Performance Measurement Method for Blind Through Silicon Vias (TSVs) in a 300 mm Wafer
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 31–June 3, pp.
1204
1210
.10.1109/ECTC.2011.5898663
128.
Lau
,
J. H.
,
Selvanayagam
,
C. S.
,
Damaruganath
,
P.
,
Hoe
,
Y. Y. G.
,
Rao
,
V. S.
,
Wai
,
E.
,
Liao
,
E. B.
, et al.,
2011
, “
Development of Large Die Fine-Pitch Cu/Low-k FCBGA Package With Through Silicon Via (TSV) Interposer
,”
IEEE Trans. CPMT
,
1
(
5
), pp.
660
672
.10.1109/TCPMT.2010.2101911
129.
Lau
,
J. H.
,
Chien
,
H. C.
, and
Tain
,
R.
,
2011
, “
TSV Interposers With Embedded Microchannels for 3D IC and LED Integration
,”
ASME
Paper No. InterPACK2011-52204. 10.1115/InterPACK2011-52204
130.
Lau
,
J. H.
,
Zhan
,
C.-J.
,
Tzeng
,
P.-J.
,
Lee
,
C.-K.
,
Dai
,
M.-J.
,
Chien
,
H.-C.
,
Chao
,
Y.-L.
, et al.,
2011
, “
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) From a 300 mm Multi-Project Wafer (MPW)
,”
IMAPS Trans., J. Microelectron. Packaging
,
8
(
4
), pp.
171
178
.10.4071/imaps.306
131.
Hsin
,
Y. C.
,
Chen
,
C.
,
Lau
,
J. H.
,
Tzeng
,
P.
,
Shen
,
S.
,
Hsu
,
Y.
,
Chen
,
S.
, et al.,
2011
, “
Effects of Etch Rate on Scallop of Through-Silicon Vias (TSVs) in 200 mm and 300 mm Wafers
,”
Proceedings of IEEE/ECTC
, Orlando, FL, May 31–June 3, pp.
1130
1135
.10.1109/ECTC.2011.5898652
132.
Sheu
,
S.-S.
,
Lin
,
Z.-H.
,
Hung
,
J.-F.
,
Lau
,
J. H.
,
Chen
,
P.-S.
,
Wu
,
S.-H.
, and
Su
,
K.-L.
,
2011
, “
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
,”
IMAPS Trans., J. Microelectron. Packaging
,
8
(
4
), pp.
140
145
.10.4071/imaps.307
133.
Lau
,
J. H.
,
2011
, “
Overview and Outlook of TSV and 3D Integrations
,”
J. Microelectron. Int.
,
28
(
2
), pp.
8
22
.10.1108/13565361111127304
134.
Lau
,
J. H.
,
2011
, “
The Most Cost-Effective Integrator (TSV Interposer) for 3D IC Integration System-in-Package (SiP)
,”
ASME
Paper No. InterPACK2011-52189. 10.1115/InterPACK2011-52189
135.
Lau
,
J. H.
, and
Zhang
,
X.
,
2011
, “
Effects of TSV Interposer on the Reliability of 3D IC Integration SiP
,”
ASME
Paper No. InterPACK2011-52205. 10.1115/InterPACK2011-52205
136.
Chaabouni
,
H.
,
Rousseau
,
M.
,
Ldeus
,
P.
,
Farcy
,
A.
,
Farhane
,
R. E.
,
Thuaire
,
A.
,
Haury
,
G.
, et al.,
2010
, “
Investigation on TSV Impact on 65 nm CMOS Devices and Circuits
,”
Proceedings of IEEE/IEDM
, San Francisco, Dec. 6–8, pp.
35.1.1
35.1.4
.10.1109/IEDM.2010.5703479
137.
Banijamali
,
B.
,
Ramalingam
,
S.
,
Nagarajan
,
K.
, and
Chaware
,
R.
,
2011
, “
Advanced Reliability Study of TSV Interposers and Interconnects for the 28 nm Technology FPGA
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 31–June 3, pp.
285
290
.10.1109/ECTC.2011.5898527
138.
Banijamali
,
B.
,
Ramalingam
,
S.
,
Kim
,
N.
,
Wyland
,
C.
,
Kim
,
N.
,
Wu
,
D.
,
Carrel
,
J.
, et al.,
2011
, “
Ceramics vs. low-CTE Organic Packaging of TSV Silicon Interposers
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 31–June 3, pp.
573
576
.10.1109/ECTC.2011.5898569
139.
Zoschke
,
K.
,
Wolf
,
J.
,
Lopper
,
C.
,
Kuna
,
I.
,
Jürgensen
,
N.
,
Glaw
,
V.
,
Samulewicz
,
K.
, et al.,
2011
, “
TSV Based Silicon Interposer Technology for Wafer Level Fabrication of 3D SiP Modules
,”
Proceedings of IEEE/ECTC
, Orlando, FL, May 3–June 3, pp.
836
842
.10.1109/ECTC.2011.5898608
140.
Lau
,
J. H.
,
2012
, “
Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry
,”
Electrochem. Soc., ECS Trans.
,
44
(
1
), pp.
805
825
.10.1149/1.3694402
141.
Chien
,
H. C.
,
Lau
,
J. H.
,
Chao
,
Y.
,
Tain
,
R.
,
Dai
,
M.
,
Wu
,
S. T.
,
Lo
,
W.
, and
Kao
,
M. J.
,
2012
, “
Thermal Performance of 3D IC Integration With Through-Silicon Via (TSV)
,”
IMAPS Trans., J. Microelectron. Packaging
,
9
(
2
), pp.
97
103
.10.4071/imaps.309
142.
Chien
,
J.
,
Lau
,
J. H.
,
Chao
,
Y.
,
Dai
,
M.
,
Tain
,
R.
,
Li
,
L.
,
Su
,
P.
, et al.,
2012
, “
Thermal Evaluation and Analyses of 3D IC Integration SiP With TSVs for Network System Applications
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1866
1873
.10.1109/ECTC.2012.6249092
143.
Chien
,
H.
,
Lau
,
J. H.
,
Chao
,
T.
,
Dai
,
M.
, and
Tain
,
R.
,
2012
, “
Thermal Management of Moore's Law Chips on Both Sides of an Interposer for 3D IC Integration SiP
,”
IEEE/ICEP Proceedings
, Tokyo, Japan, Apr. 4–6, pp.
38
44
.
144.
Zhan
,
C.
,
Tzeng
,
P.
,
Lau
,
J. H.
,
Dai
,
M.
,
Chien
,
H.
,
Lee
,
C.
,
Wu
,
S.
, et al.,
2012
, “
Assembly Process and Reliability Assessment of TSV/RDL/IPD Interposer With Multi-Chip-Stacking for 3D IC Integration SiP
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
548
554
.10.1109/ECTC.2012.6248883
145.
Tzeng
,
P.
,
Lau
,
J. H.
,
Dai
,
M.
,
Wu
,
S.
,
Chien
,
H.
,
Chao
,
Y.
,
Chen
,
C.
, et al.,
2012
, “
Design, Fabrication, and Calibration of Stress Sensors Embedded in a TSV Interposer in a 300 mm Wafer
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1731
1737
.10.1109/ECTC.2012.6249071
146.
Lee
,
C. K.
,
Chang
,
T. C.
,
Lau
,
J. H.
,
Huang
,
Y.
,
Fu
,
H.
,
Huang
,
J.
,
Hsiao
,
Z.
, et al.,
2012
, “
Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration
,”
IEEE Trans. CPMT
,
2
(
8
), pp.
1229
1238
.10.1109/TCPMT.2012.2189397
147.
Chen
,
J. C.
,
Lau
,
J. H.
,
Tzeng
,
P. J.
,
Chen
,
S.
,
Wu
,
C.
,
Chen
,
C.
,
Yu
,
H.
, et al.,
2012
, “
Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration
,”
IEEE Trans. CPMT
,
2
(
6
), pp.
956
963
.10.1109/TCPMT.2011.2177663
148.
Lau
,
J. H.
, and
Tang
,
G. Y.
,
2012
, “
Effects of TSVs (Through-Silicon Vias) on Thermal Performances of 3D IC Integration System-in-Package (SiP)
,”
J. Microelectron. Reliab.
,
52
(
11
), pp.
2660
2669
.10.1016/j.microrel.2012.04.002
149.
Lau
,
J. H.
,
Wu
,
S. T.
, and
Chien
,
H. C.
,
2012
, “
Nonlinear Analyses of Semi-Embedded Through-Silicon Via (TSV) Interposer With Stress Relief Gap Under Thermal Operating and Environmental Conditions
,”
IEEE EuroSime Proceedings
, Lisbon, Portugal, Apr. 16–18, pp.
1/6
6/6
.10.1109/ESimE.2012.6191796
150.
Wu
,
C.
,
Chen
,
S.
,
Tzeng
,
P.
,
Lau
,
J. H.
,
Hsu
,
Y.
,
Chen
,
J.
,
Hsin
,
Y.
, et al.,
2012
, “
Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration
,”
IMAPS Trans., J. Microelectron. Packaging
,
9
(
1
), pp.
31
36
.10.4071/imaps.308
151.
Li
,
L.
,
Su
,
P.
,
Xue
,
J.
,
Brillhart
,
M.
,
Lau
,
J. H.
,
Tzeng
,
P.
,
Lee
,
C.
, et al.,
2012
, “
Addressing Bandwidth Challenges in Next Generation High Performance Network Systems With 3D IC Integration
,”
IEEE ECTC Proceedings
,
San Diego, CA
, May 29–June 1, pp.
1040
1046
.10.1109/ECTC.2012.6248964
152.
Lau
,
J. H.
,
2012
, “
Supply Chains for 3D IC Integration Manufacturing
,”
Proceedings of IEEE Electronic Materials and Packaging Conference
, Hong Kong, China, Dec. 13–16, pp.
72
78
.10.1109/EMAP.2012.6507848
153.
Lau
,
J. H.
,
Wu
,
S. T.
, and
Chien
,
H. C.
,
2012
, “
Thermal-Mechanical Responses of 3D IC Integration With a Passive TSV Interposer
,”
IEEE EuroSime Proceedings
,
Lisbon, Portugal
, Apr. 16–18, pp.
1/8
8/8
.10.1109/ESimE.2012.6191797
154.
Chai
,
T. C.
,
Zhang
,
X.
,
Li
,
H.
,
Sekhar
,
V.
,
Kalandar
,
O.
,
Khan
,
N.
,
Lau
,
J. H.
, et al.,
2012
, “
Impact of Packaging Design on Reliability of Large Die Cu/Low-κ (BD) Interconnect
,”
IEEE Trans. CPMT
,
2
(
5
), pp.
807
816
.10.1109/TCPMT.2011.2182351
155.
Sekhar
,
V. N.
,
Shen
,
L.
,
Kumar
,
A.
,
Chai
,
T. C.
,
Zhang
,
X.
,
Premchandran
,
C. S.
,
Kripesh
,
V.
, et al.,
2012
, “
Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-k Stack
,”
IEEE Trans. CPMT
,
2
(
1
), pp.
3
12
.10.1109/TCPMT.2011.2141989
156.
Chaware
,
R.
,
Nagarajan
,
K.
, and
Ramalingam
,
S.
,
2012
, “
Assembly and Reliability Challenges in 3D Integration of 28 nm FPGA Die on a Large High Density 65 nm Passive Interposer
,”
Proceedings of IEEE/ECTC
,
San Diego, CA
, May 29–June 1, pp.
279
283
.10.1109/ECTC.2012.6248841
157.
Banijamali
,
B.
,
Ramalingam
,
S.
,
Liu
,
H.
, and
Kim
,
M.
,
2012
, “
Outstanding and Innovative Reliability Study of 3D TSV Interposer and Fine Pitch Solder Micro-Bumps
,”
Proceedings of IEEE/ECTC
,
San Diego, CA
, May 29–June 1, pp.
309
314
.10.1109/ECTC.2012.6248847
158.
Kim
,
N.
,
Wu
,
D.
,
Carrel
,
J.
,
Kim
,
J.
, and
Wu
,
P.
,
2012
, “
Channel Design Methodology for 28 Gb/s SerDes FPGA Applications With Stacked Silicon Interconnect Technology
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1786
1793
.10.1109/ECTC.2012.6249080
159.
Li
,
Z.
,
Shi
,
H.
,
Xie
,
J.
, and
Rahman
,
A.
,
2012
, “
Development of an Optimized Power Delivery System for 3D IC Integration With TSV Silicon Interposer
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 29–June 1, pp.
678
682
.10.1109/ECTC.2012.6248905
160.
Khan
,
N.
,
Li
,
H.
,
Tan
,
S.
,
Ho
,
S.
,
Kripesh
,
V.
,
Pinjala
,
D.
,
Lau
,
J. H.
, and
Chuan
,
T.
,
2013
, “
3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections
,”
IEEE Trans. CPMT
,
3
(
2
), pp.
221
228
.10.1109/TCPMT.2012.2186297
161.
Lau
,
J. H.
,
Tzeng
,
P.
,
Lee
,
C.
,
Zhan
,
C.
,
Li
,
M.
,
Cline
,
J.
, and
Saito
,
K.
, et al.,
2013
, “
Redistribution Layers (RDLs) for 2.5D/3D IC Integration
,”
Proceedings of the 46th IMAPS International Symposium on Microelectronics
, Orlando, FL, Sept. 30–Oct. 3, pp.
434
441
.10.4071/isom-2013-WA12
162.
Wu
,
S. T.
,
Chien
,
H.
,
Lau
,
J. H.
,
Li
,
M.
,
Cline
,
J.
, and
Ji
,
M.
,
2013
, “
Thermal and Mechanical Design and Analysis of 3D IC Interposer With Double-Sided Active Chips
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1471
1479
.10.1109/ECTC.2013.6575766
163.
Tzeng
,
P. J.
,
Lau
,
J. H.
,
Zhan
,
C.
,
Hsin
,
Y.
,
Chang
,
P.
,
Chang
,
Y.
,
Chen
,
J.
, et al.,
2013
, “
Process Integration of 3D Si Interposer With Double-Sided Active Chip Attachments
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
86
93
.10.1109/ECTC.2013.6575555
164.
Lee
,
C. C.
,
Yang
,
T. F.
,
Wu
,
C. S.
,
Kao
,
K. S.
,
Fang
,
C. W.
,
Zhan
,
C. J.
,
Lau
,
J. H.
, and
Chen
,
T. H.
,
2013
, “
Impact of High Density TSVs on the Assembly of 3D-ICs Packaging
,”
Microelectron. Eng.
,
107
, pp.
101
106
.10.1016/j.mee.2012.09.011
165.
Chen
,
J.
,
Lau
,
J. H.
,
Hsu
,
T.
,
Chen
,
C.
,
Tzeng
,
P.
,
Chang
,
P.
,
Chien
,
C.
, et al.,
2013
, “
Challenges of Cu CMP of TSVs and RDLs Fabricated From the Backside of a Thin Wafer
,”
IEEE International 3D Systems Integration Conference
, San Francisco, CA, Oct. 2–4, pp.
1
5
.
10.1109/3DIC.2013.6702335
166.
Banijamali
,
B.
,
Chiu
,
C.
,
Hsieh
,
C.
,
Lin
,
T.
,
Hu
,
C.
,
Hou
,
S.
,
Ramalingam
,
S.
,
Jeng
,
S.
,
Madden
,
L.
, and
Yu
,
D.
,
2013
, “
Reliability Evaluation of a CoWoS-Enabled 3D IC Package
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
35
40
.10.1109/ECTC.2013.6575547
167.
Hariharan
,
G.
,
Chaware
,
R.
,
Yip
,
L.
,
Singh
,
I.
,
Ng
,
K.
,
Pai
,
S.
,
Kim
,
M.
, et al.,
2013
, “
Assembly Process Qualification and Reliability Evaluations for Heterogeneous 2.5D FPGA With HiCTE Ceramic
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
904
908
.10.1109/ECTC.2013.6575681
168.
Lau
,
J. H.
,
Tzeng
,
P.
,
Lee
,
C.
,
Zhan
,
C.
,
Li
,
M.
,
Cline
,
J.
,
Saito
,
K.
, et al.,
2014
, “
Redistribution Layers (RDLs) for 2.5D/3D IC Integration
,”
IMAPS Trans., J. Microelectron. Packaging
,
11
(
1
), pp.
16
24
.10.4071/imaps.406
169.
Lau
,
J. H.
,
Lee
,
C.
,
Zhan
,
C.
,
Wu
,
S.
,
Chao
,
Y.
,
Dai
,
M.
,
Tain
,
R.
, et al.,
2014
, “
Low-Cost TSH (Through-Silicon Hole) Interposers for 3D IC Integration
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 27–30, pp.
290
296
.
170.
Lau
,
J. H.
,
Lee
,
C.
,
Zhan
,
C.
,
Wu
,
S.
,
Chao
,
Y.
,
Dai
,
M.
,
Tain
,
R.
, et al.,
2014
, “
Low-Cost Through-Silicon Hole Interposers for 3D IC Integration
,”
IEEE Trans. CPMT
,
4
(
9
), pp.
1407
1419
.10.1109/ECTC.2014.6897301
171.
Hsieh
,
M. C.
,
Wu
,
S. T.
,
Wu
,
C. J.
, and
Lau
,
J. H.
,
2014
, “
Energy Release Rate Estimation for Through Silicon Vias in 3-D Integration
,”
IEEE Trans. CPMT
,
4
(
1
), pp.
57
65
.10.1109/TCPMT.2013.2283503
172.
Lau
,
J. H.
,
2014
, “
Overview and Outlook of 3D IC Packaging, 3D IC Integration, and 3D Si Integration ASME Transactions
,”
ASME J. Electron. Packaging
,
136
(
4
), pp.
1
15
.10.1115/1.4028629
173.
Banijamali
,
B.
,
Lee
,
T.
,
Liu
,
H.
,
Ramalingam
,
S.
,
Barber
,
I.
,
Chang
,
J.
,
Kim
,
M.
, and
Yip
,
L.
,
2015
, “
Reliability Evaluation of an Extreme TSV Interposer and Interconnects for the 20 nm Technology CoWoS IC Package
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 26–29, pp.
276
280
.10.1109/ECTC.2015.7159604
174.
Hariharan
,
G.
,
Chaware
,
R.
,
Singh
,
I.
,
Lin
,
J.
,
Yip
,
L.
,
Ng
,
K.
, and
Pai
,
S.
,
2015
, “
A Comprehensive Reliability Study on a CoWoS 3D IC Package
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 26–29, pp.
573
577
.10.1109/ECTC.2015.7159648
175.
Ma
,
M.
,
Chen
,
S.
,
Lai
,
J.
,
Lu
,
T.
,
Chen
,
A.
,
Lin
,
G.
,
Lu
,
C.
,
Liu
,
C.
, and
Peng
,
S.
,
2016
, “
Development and Technological Comparison of Various Die Stacking and Integration Options With TSV Si Interposer
,”
IEEE/ECTC Proceedings
, Las Vegas, NA, May 31–June 3, pp.
336
342
.10.1109/ECTC.2016.148
176.
AMD,
2015
, “The AMD Radeon R9 Fury X Review,” AMD, Santa Clara, CA, accessed Oct. 2020, https://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/2
177.
Hou
,
S.
,
Chen
,
W.
,
Hu
,
C.
,
Chiu
,
C.
,
Ting
,
K.
,
Lin
,
T.
,
Wei
,
W.
,
Chiou
,
W.
, et al.,
2017
, “
Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
,”
IEEE Trans. Electron Devices
,
64
(
10
), pp.
4071
4077
.10.1109/TED.2017.2737644
178.
Lai
,
C.
,
Li
,
H.
,
Peng
,
S.
,
Lu
,
T.
, and
Chen
,
S.
,
2017
, “
Warpage Study of Large 2.5D IC Chip Module
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 30–June 2, pp.
1263
1268
.10.1109/ECTC.2017.210
179.
Shih
,
M.
,
Hsu
,
C.
,
Chang
,
Y.
,
Chen
,
K.
,
Hu
,
I.
,
Lee
,
T.
,
Tarng
,
D.
, and
Hung
,
C.
,
2017
, “
Warpage Characterization of Glass Interposer Package Development
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 30–June 2, pp.
1392
1397
.10.1109/ECTC.2017.110
180.
Agrawal
,
A.
,
Huang
,
S.
,
Gao
,
G.
,
Wang
,
L.
,
DeLaCruz
,
J.
, and
Mirkarimi
,
L.
,
2017
, “
Thermal and Electrical Performance of Direct Bond Interconnect Technology for 2.5D and 3D Integrated Circuits
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 30–June 2, pp.
989
998
.10.1109/ECTC.2017.341
181.
Choi
,
S.
,
Park
,
J.
,
Jung
,
D.
,
Kim
,
J.
,
Kim
,
H.
, and
Kim
,
K.
,
2017
, “
Signal Integrity Analysis of Silicon/Glass/Organic Interposers for 2.5D/3D Interconnects
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 30–June 2, pp.
2139
2144
.10.1109/ECTC.2017.160
182.
Ravichandran
,
S.
,
Yamada
,
S.
,
Park
,
G.
,
Chen
,
H.
,
Shi
,
T.
,
Buch
,
C.
,
Liu
,
F.
,
Smet
,
V.
, et al.,
2018
, “
2.5D Glass Panel Embedded (GPE) Packages With Better I/O Density, Performance, Cost and Reliability Than Current Silicon Interposers and High-Density Fan-Out Packages
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
625
630
.10.1109/ECTC.2018.00099
183.
Wang
,
J.
,
Niu
,
Y.
,
Park
,
S.
, and
Yatskov
,
A.
,
2018
, “
Modeling and Design of 2.5D Package With Mitigated Warpage and Enhanced Thermo-Mechanical Reliability
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
2471
2477
.10.1109/ECTC.2018.00373
184.
Okamoto
,
D.
,
Shibasaki
,
Y.
,
Shibata
,
D.
,
Hanada
,
T.
,
Liu
,
F.
,
Sundaram
,
V.
, and
Tummala
,
R.
,
2018
, “
An Advanced Photosensitive Dielectric Material for High-Density RDL With Ultra-Small Photo-Vias and Ultra-Fine Line/Space in 2.5D Interposers and Fan-Out Packages
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1543
1548
.10.1109/ECTC.2018.00234
185.
Cai
,
H.
,
Ma
,
S.
,
Zhang
,
J.
,
Xiang
,
W.
,
Wang
,
W.
,
Jin
,
Y.
,
Chen
,
J.
,
Hu
,
L.
, and
He
,
S.
,
2018
, “
Thermal and Electrical Characterization of TSV Interposer Embedded With Microchannel for 2.5D Integration of GaN RF Devices
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
2150
2156
.10.1109/ECTC.2018.00323
186.
Hong
,
J.
,
Choi
,
K.
,
Oh
,
D.
,
Shao
,
S.
,
Wang
,
H.
,
Niu
,
Y.
, and
Pham
,
V.
,
2018
, “
Design Guideline of 2.5D Package With Emphasis on Warpage Control and Thermal Management
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
682
692
.10.1109/ECTC.2018.00108
187.
Nair
,
C.
,
DeProspo
,
B.
,
Hichri
,
H.
,
Arendt
,
M.
,
Liu
,
F.
,
Sundaram
,
V.
, and
Tummala
,
R.
,
2018
, “
Reliability Studies of Excimer Laser-Ablated Microvias Below 5 Micron Diameter in Dry Film Polymer Dielectrics for Next Generation, Panel-Scale 2.5D Interposer RDL
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
1005
1009
.10.1109/ECTC.2018.00154
188.
Xu
,
J.
,
Niu
,
Y.
,
Cain
,
S.
,
McCann
,
S.
,
Lee
,
H.
,
Ahmed
,
G.
, and
Park
,
S.
,
2018
, “
The Experimental and Numerical Study of Electromigration in 2.5D Packaging
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
483
489
.10.1109/ECTC.2018.00077
189.
McCann
,
S.
,
Lee
,
H.
,
Ahmed
,
G.
,
Lee
,
T.
, and
Ramalingam
,
S.
,
2018
, “
Warpage and Reliability Challenges for Stacked Silicon Interconnect Technology in Large Packages
,”
IEEE/ECTC Proceedings
, San Diego, CA, May 29–June 1, pp.
2339
2344
.10.1109/ECTC.2018.00353
190.
Hsiao
,
Y.
,
Hsu
,
C.
,
Lin
,
Y.
, and
Chien
,
C.
,
2019
, “
Reliability and Benchmark of 2.5D Non-Molding and Molding Technologies
,”
IEEE/ECTC Proceedings
, Las Vegas, NA, May 28–31, pp.
461
466
.10.1109/ECTC.2019.00076
191.
Pares
,
G.
,
Michel
,
J.
,
Deschaseaux
,
E.
,
Ferris
,
P.
,
Serhan
,
A.
, and
Giry
,
A.
,
2019
, “
Highly Compact RF Transceiver Module Using High Resistive Silicon Interposer With Embedded Inductors and Heterogeneous Dies Integration
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1279
1286
.10.1109/ECTC.2019.00198
192.
Okamoto
,
D.
,
Shibasaki
,
Y.
,
Shibata
,
D.
,
Hanada
,
T.
,
Liu
,
F.
,
Kathaperumal
,
M.
, and
Tummala
,
R.
,
2019
, “
Fabrication and Reliability Demonstration of 3 μm Diameter Photo Vias at 15 μm Pitch in Thin Photosensitive Dielectric Dry Film for 2.5 D Glass Interposer Applications
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
2112
2116
.10.1109/ECTC.2019.00-31
193.
Wang
,
H.
,
Wang
,
J.
,
Xu
,
J.
,
Pham
,
V.
,
Pan
,
K.
,
Park
,
S.
,
Lee
,
H.
, and
Ahmed
,
G.
,
2019
, “
Product Level Design Optimization for 2.5D Package Pad Cratering Reliability During Drop Impact
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
2343
2348
.10.1109/ECTC.2019.00323
194.
Chen
,
W.
,
Lin
,
C.
,
Tsai
,
C.
,
Hsia
,
H.
,
Ting
,
K.
,
Hou
,
S.
,
Wang
,
C.
, and
Yu
,
D.
,
2020
, “
Design and Analysis of Logic-HBM2E Power Delivery System on CoWoS® Platform With Deep Trench Capacitor
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
380
385
.10.1109/ECTC32862.2020.00068
195.
Bhuvanendran
,
S.
,
Gourikutty
,
N.
,
Chua
,
K.
,
Alton
,
J.
,
Chinq
,
J.
,
Umralkar
,
R.
,
Chidambaram1
,
V.
, and
Bhattacharya
,
S.
,
2020
, “
Non-Destructive Fault Isolation in Through-Silicon Interposer Based System in Package
,”
IEEE/EPTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
281
285
.10.1109/EPTC50525.2020.9315038
196.
Sirbu
,
B.
,
Eichhammer
,
Y.
,
Oppermann
,
H.
,
Tekin
,
T.
,
Kraft
,
J.
,
Sidorov
,
V.
,
Yin
,
X.
, et al.,
2019
, “
3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers With Double-Side Assembled Active Components and Integrated Optical and Electrical Through Silicon Via on SOI
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1052
1059
.10.1109/ECTC.2019.00165
197.
Iwai
,
T.
,
Sakai
,
T.
,
Mizutani
,
D.
,
Sakuyama
,
S.
,
Iida
,
K.
,
Inaba
,
T.
,
Fujisaki
,
H.
, et al.,
2019
, “
Multilayer Glass Substrate With High Density Via Structure for All Inorganic Multi-Chip Module
,”
IEEE/ECTC Proceedings
, Las Vegas, NV, May 28–31, pp.
1952
1957
.10.1109/ECTC.2019.00301
198.
Tanaka
,
M.
,
Kuramochi
,
S.
,
Dai
,
T.
,
Sato
,
Y.
, and
Kidera
,
N.
,
2020
, “
High Frequency Characteristics of Glass Interposer
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
601
610
.10.1109/ECTC32862.2020.00100
199.
Ding
,
Q.
,
Liu
,
H.
,
Huan
,
Y.
, and
Jiang
,
J.
,
2020
, “
High Bandwidth Low Power 2.5D Interconnect Modeling and Design
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
1832
1837
.10.1109/ECTC32862.2020.00286
200.
Kim
,
M.
,
Liu
,
H.
,
Klokotov
,
D.
,
Wong
,
A.
,
To
,
T.
, and
Chang
,
J.
,
2020
, “
Performance Improvement for FPGA Due to Interposer Metal Insulator Metal Decoupling Capacitors (MIMCAP)
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
386
392
.10.1109/ECTC32862.2020.00069
201.
Bhuvanendran
,
S.
,
Gourikutty
,
N.
,
Chow
,
Y.
,
Alton
,
J.
,
Umralkar
,
R.
,
Bai
,
H.
,
Chua
,
K.
, and
Bhattacharya
,
S.
,
2020
, “
Defect Localization in Through-Si-Interposer Based 2.5D ICs
,”
IEEE/ECTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
1180
1185
.10.1109/ECTC32862.2020.00189
202.
Wang
,
X.
,
Ren
,
Q.
, and
Kawano
,
M.
,
2020
, “
Yield Improvement of Silicon Trench Isolation for One-Step TSV
,”
IEEE/EPTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
22
26
.10.1109/EPTC50525.2020.9315080
203.
Ren
,
Q.
,
Loh
,
W.
,
Neo
,
S.
, and
Chui
,
K.
,
2020
, “
Temporary Bonding and De-Bonding Process for 2.5D/3D Applications
,”
IEEE/EPTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
27
31
.10.1109/EPTC50525.2020.9315033
204.
Chuan
,
P.
, and
Tan
,
S.
,
2020
, “
Glass Substrate Interposer for TSV-Integrated Surface Electrode Ion Trap
,”
IEEE/EPTC Proceeding
, Lake Buena Vista, FL, May 26–29, pp.
262
265
.10.1109/EPTC50525.2020.9315003
205.
Loh
,
W.
, and
Chui
,
K.
,
2020
, “
Wafer Warpage Evaluation of Through Si Interposer (TSI) With Different Temporary Bonding Materials
,”
IEEE/EPTC Proceedings
, Lake Buena Vista, FL, May 26–29, pp.
268
272
.10.1109/EPTC50525.2020.9315102
206.
Hicks
,
J.
,
Malta
,
D.
,
Bordelon
,
D.
,
Richter
,
D.
,
Hong
,
J.
,
Grindlay
,
J.
, and
Allen
,
B.
,
2021
, “
TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
170
177
.10.1109/ECTC32696.2021.00038
207.
Song
,
E.
,
Oh
,
D.
,
Cha
,
S.
,
Jang
,
J.
,
Hwang
,
T.
,
Kim
,
G.
, and
Kim
,
J.
,
2020
, “
Power Integrity Performance Gain of a Novel Integrated Stack Capacitor (ISC) Solution for High-End Computing Applications
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 26–29, pp.
1358
1362
.10.1109/ECTC32862.2020.00215
208.
Kawano
,
M.
,
Wang
,
X.
,
Ren
,
Q.
,
Loh
,
W.
,
Rao
,
B.
, and
Chui
,
K.
,
2021
, “
One-Step TSV Process Development for 4-Layer Wafer Stacked DRAM
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
673
679
.10.1109/ECTC32696.2021.00117
209.
Kim
,
T.
,
Cho
,
S.
,
Hwang
,
S.
,
Lee
,
K.
,
Hong
,
Y.
,
Lee
,
H.
,
Cho
,
H.
, et al.,
2021
, “
Multi-Stack Wafer Bonding Demonstration Utilizing Cu to Cu Hybrid Bonding and TSV Enabling Diverse 3D Integration
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 26–29, pp.
415
419
.10.1109/ECTC32696.2021.00076
210.
Hu
,
L.
,
Chen
,
C.
,
Lin
,
M.
,
Lin
,
C.
,
Yeh
,
C.
,
Kuo
,
C.
,
Lin
,
T.
, and
Hsu
,
S.
,
2021
, “
Pre-Bond Qualification of Through-Silicon Via for the Application of 3-D Chip Stacking
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 26–29, pp.
285
291
.10.1109/ECTC32696.2021.00055
211.
Zhang
,
X.
,
Lin
,
J.
,
Wickramanayaka
,
S.
,
Zhang
,
S.
,
Weerasekera
,
R.
,
Dutta
,
R.
,
Chang
,
K.
, et al.,
2015
, “
Heterogeneous 2.5D Integration on Through Silicon Interposer
,”
Appl. Phys. Rev.
,
2
(
2
), p.
021308
.10.1063/1.4921463
212.
Jalilvand
,
G.
,
Lindsay
,
J.
,
Reidy
,
B.
,
Shukla
,
V.
,
Duggan
,
D.
,
Zand
,
R.
, and
Jiang
,
T.
,
2021
, “
Application of Machine Learning in Recognition and Analysis of TSV Extrusion Profiles With Multiple Morphology
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1652
1659
.10.1109/ECTC32696.2021.00262
213.
Huang
,
P.
,
Lu
,
C.
,
Wei
,
W.
,
Chui
,
C.
,
Ting
,
K.
,
Hu
,
C.
,
Tsai
,
C.
, et al.,
2021
, “
Wafer Level System Integration of the Fifth Generation CoWoS®-S With High Performance Si Interposer at 2500 mm2
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
101
104
.10.1109/ECTC32696.2021.00028
214.
Funaki
,
T.
,
Satake
,
Y.
,
Kobinata
,
K.
,
Hsiao
,
C.
,
Matsuno
,
H.
,
Ahe
,
S.
,
Kim
,
Y.
, and
Ohba
,
T.
,
2021
, “
Miniaturized 3D Functional Interposer Using Bumpless Chip-on-Wafer (COW) Integration With Capacitors
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
185
190
.10.1109/ECTC32696.2021.00040
215.
Zhao
,
P. H.
,
Li
,
J.
,
Tao
,
Y.
,
Lim
,
W.
,
Seit
,
L.
,
Guidoni
., and
Tan
,
C.
,
2021
, “
Heterogeneous Integration of Silicon Ion Trap and Glass Interposer or Scalable Quantum Computing Enabled by TSV, Micro-Bumps and RDL
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
279
284
.10.1109/ECTC32696.2021.00054
216.
Moon
,
J.
,
Shin
,
Y.
,
Kim
,
S.
,
Hahn
,
S.
,
Lim
,
K.
,
Jung
,
J.
,
Lim
,
C.
,
Kim
,
Y.
,
Hwang
,
J.
, and
Rhee
,
M.
,
2021
, “
Non-Conductive Film Analysis Using Cure Kinetics and Rheokinetics for Gang Bonding Process for 3DIC TSV Packaging
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
706
710
.10.1109/ECTC32696.2021.00122
217.
Son
,
J.
,
Moon
,
S.
,
Nam
,
S.
, and
Kim
,
W.
,
2021
, “
PI/SI Consideration for Enabling 3D IC Design
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1307
1311
.10.1109/ECTC32696.2021.00211
218.
Han
,
M.
,
Shin
,
Y.
,
Lim
,
K.
, and
Rhee
,
D.
,
2021
, “
A Development of Finite Element Analysis Model of 3DIC TSV Package Warpage Considering Cure Dependent Viscoelasticity With Heat Generation
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1475
1580
.10.1109/ECTC32696.2021.00235
219.
Lee
,
S. S.
,
Han
,
J.
,
Hong
,
S. O.
,
Kwak
,
D.
,
Nam
,
S.
,
Park
,
Y.
, and
Lee
,
J.
,
2021
, “
Novel Method of Wafer-Level and Package-Level Process Simulation for Warpage Optimization of 2.5D TSV
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1527
1531
.10.1109/ECTC32696.2021.00242
220.
Kim
,
S.
,
Kim
,
H.
,
Hong
,
J.
,
Kwon
,
O.
, and
Lee
,
H.
,
2021
, “
Process Optimization of Micro Bump Pitch Design in 3-Dimensional Package Structure
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1870
1875
.10.1109/ECTC32696.2021.00295
221.
Satake
,
Y.
,
Funaki
,
T.
,
Kobinata
,
K.
,
Matsuno
,
H.
,
Hidaka
,
S.
,
Abe
,
S.
,
Ito
,
H.
, et al.,
2022
, “
Functional Interposer Embedded With Multi-Terminal Si Capacitor for 2.5D/3D Applications Using Planarization and Bumpless Chip-on-Wafer (COW)
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
283
288
.10.1109/ECTC51906.2022.00053
222.
Patti
,
R.
,
2023
, “Building Advanced 3D Devices With Hybrid Bonding,” Proceeding of WLPS, Milpitas, CA, Feb., pp. 39–45.
223.
Nelson
,
S.
,
Levy
,
D.
, and
Tutt
,
L.
,
2023
, “Wafer and Panel Handing for Thin Glass Interposers,” Proceeding of WLPS, Milpitas, CA, Feb., pp. 66–69.
224.
Shehzad
,
A.
,
Yin
,
R.
,
Panchenko
,
I.
,
Muller
,
M.
,
Bickel
,
S.
,
Birlem
,
O.
,
Quednau
,
S.
, and
Wolf
,
J.
,
2022
, “Novel Cu-Nanowires-Based Technology Enabling Fine Pitch Interconnects for 2.5D/3D Integration,” Proceedings of ESTC, Sibiu, Romania, Sept., pp. 118–123.
225.
Moore
,
S.
,
2022
, “
Graphcore Uses TSMC 3D Chip Tech to Speed AI by 40%
,”
IEEE Spectrum
, Mar. 3, pp.
1
3
.
226.
Sato
,
M.
, April
2022
, “
The Supercomputer “Fugaku
,”
Proceedings of IEEE/VLSI-DAT
, Hsinchu, Taiwan, Apr. 18–21, pp.
1
1
.
227.
Samsung Newsroom,
2021
, “
Samsung Electronics Announces Availability of Its Next Generation 2.5D Integration Solution ‘I-Cube4’ for High-Performance Applications
,” May 6.
228.
Samsung Newsroom,
2021
, “
Leading-Edge 2.5D Integration ‘H-Cube’ Solution for High Performance Applications
,” Nov. 11.
229.
Nam
,
S.
,
Kim
,
Y.
,
Jang
,
A.
,
Hwang
,
I.
,
Park
,
S.
,
Lee
,
S.
, and
Kim
,
D.
,
2021
, “
The Extremely Large 2.5D Molded Interposer on Substrate (MIoS) Package Integration - Warpage and Reliability
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
1998
2002
.10.1109/ECTC32696.2021.00315
230.
Nam
,
S.
,
Kang
,
J.
,
Lee
,
I.
,
Kim
,
Y.
,
Yu
,
H.
, and
Kim
,
D.
,
2022
, “
Investigation on Package Warpage and Reliability of the Large Size 2.5D Molded Interposer on Substrate (MIoS) Package
,”
Proceedings of IEEE/ECTC
, San Diego, CA, May 31–June 3, pp.
643
647
.10.1109/ECTC51906.2022.00108
231.
Sakuma
,
K.
,
Farooq
,
M.
,
Andry
,
P.
,
Cabral
,
C.
,
Rajalingam
,
S.
,
McHerron
,
D.
,
Li
,
S.
, et al.,
2021
, “
3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55 μm - 75 μm Mixed Pitch Interconnections on High Density Laminate
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
292
297
.10.1109/ECTC32696.2021.00056
232.
Sakuma
,
K.
,
Parekh
,
D.
,
Belyansky
,
M.
,
Gomez
,
J.
,
Skordas
,
S.
,
McHerron
,
D.
,
Sousa
,
I.
, et al.,
2021
, “
Plasma Activated Low-Temperature Die-Level Direct Dicing Technologies for 3D Heterogeneous Integration
,”
Proceedings of IEEE/ECTC
, Virtual conference, June 1–4, pp.
408
414
.10.1109/ECTC32696.2021.00075
233.
Ravichandran
,
S.
,
Kathaperumal
,
M.
,
Swaminathan
,
M.
, and
Tummala
,
R.
,
2020
, “
Large-Body-Sized Glass-Based Active Interposer for High-Performance Computing
,”
Proceedings of IEEE/ECTC
, Lake Buena Vista, FL, May 26–29, pp.
879
884
.10.1109/ECTC32862.2020.00144