This review introduces relevant nanoscale thermal transport processes that impact thermal abatement in power electronics applications. Specifically, we highlight the importance of nanoscale thermal transport mechanisms at each layer in material hierarchies that make up modern electronic devices. This includes those mechanisms that impact thermal transport through: (1) substrates, (2) interfaces and two-dimensional materials, and (3) heat spreading materials. For each material layer, we provide examples of recent works that (1) demonstrate improvements in thermal performance and/or (2) improve our understanding of the relevance of nanoscale thermal transport across material junctions. We end our discussion by highlighting several additional applications that have benefited from a consideration of nanoscale thermal transport phenomena, including radio frequency (RF) electronics and neuromorphic computing.
This review discusses relevant nanoscale thermal transport processes impacting thermal abatement in power electronics applications. In the introduction section, the impact of nanoscale thermal transport on electronics thermal management is established, and a primer is given on the physics governing nanoscale thermal transport. With core concepts established, several brief perspectives are provided on relevant topics dealing with nanoscale thermal transport in power electronics. Figure 1 depicts the organization of the contents of this paper .
1.1 Impact on Electronics Thermal Management.
Electronics thermal management is critical to the implementation of modern computational architectures , power electronics , rewriteable media  and, more recently, data storage and transfer [4,5]. Increasingly at odds with continued advancements in the performance of such applications, however, is a reduction in the characteristic length scales of heat generating elements that support primary functionality. The magnitude of this singular issue is now widely expected to result in the violation of Moore's law within the next decade, captured by Fig. 2 and described below.
Moore's law has remained stable for nearly five decades, principally due to advancements in cooling technologies and simultaneous improvements in computational efficiency with developments in parallel processing, graphics processing unit architectures and, more recently, three-dimensional (3D) chip stacks . However, both computational efficiency and cooling technologies are beginning to approach their fundamental limits . Consequently, Moore's law for conventional CMOS-based architectures is predicted by some to run its course within the next decade [13–15].
Beyond these fundamental limits, the size of individual electronic components is fast approaching length scales that are of the order of the primary mean free paths of thermal energy carriers. Fin field effect transistors (FinFET) technologies, for example, are generally expected to result in the fabrication of 3 nm transistors in the near future , orders of magnitude smaller than the majority of thermal carrier mean free paths in silicon . As thermal management is concerned, the physics that govern heat dissipation within a material and across an interface are not the same as those experienced in bulk material systems. At these length scales, the physics that govern heat dissipation within a material and across interfaces deviate significantly from bulk thermal properties.
Accordingly, when exploring the thermal impact of electronic size scaling, we need to consider the nanoscale properties of the thermal carriers carefully. At these scales, heat energy carriers (primarily phonons in nonconducting materials) can be interrupted by atomic defects, phonon–phonon interactions, nanoparticles, grain boundaries, material mismatches in phonon density of states at a boundary and, in electrically conducting materials, electron–phonon and electron–interface interactions . Figure 3 illustrates the variety of phonon scattering mechanisms that govern thermal transport at these length scales.
Given the level of complexity associated with nanoscale thermal transport physics and the scattering mechanisms outlined in Fig. 3, it is critical to understand and model these energy exchange and transfer mechanisms for the successful development and implementation of next-generation electronics devices. In this work, we specifically focus on nanoscale thermal transport in next-generation micro-electronic devices.
To demonstrate the key areas where phonon scattering plays a critical role in electronics packaging, we consider a typical electronic package configuration. This is depicted in Fig. 4, together with a representative temperature distribution of the device, which depends on the thermal resistance of each constituent element. The device comprised several layers of differing materials, interfaces between those materials, and a bulk substrate. The devices are packaged on die attached via thermal interface materials and are then coupled to a heat sink. Each of these components in the package contain opportunities for nanoscale thermal transport to provide a substantial enhancement in device performance. At the device level, the interfaces and small scale of the devices make nanoscale thermal metrology crucial for further development—whether the goal is to reach higher power or to continue trends in device miniaturization. At the package level, nanoscale thermal transport is necessary to understand what makes a better thermal interface material, or how to remove heat from the package at the heat sink effectively. Furthermore, the materials used may see reduction in phonon scattering by removing scattering sites such as defects and dislocations via improved processing parameters, thus increasing the thermal conductivity of the layer adjacent to the interface. Therefore, in the electronics package, from material level to device level to packaging level, nanoscale thermal transport is critical to further advances in performance.
In this work, we put forth a series of perspectives constructed by the authors to highlight the nanoscale thermal physics used to model scattering mechanisms within materials and across interfaces. In particular, we provide the reader with analytical and numerical techniques that lend physical insight into heat flow through materials and interfaces that are critical in electronics packaging and discuss experimental evidence of these consequences in application. A final discussion of nanoscale thermal transport in radio frequency (RF)-based devices and thermoelectric materials is provided to demonstrate the broad class of application space where these physics are critical to electronic device performance and cooling.
1.2 Nanoscale Thermal Physics.
In the ensuing sections, we provide a limited overview of the physics that are typically used to analytically model thermal transport both (a) within materials and (b) across device interfaces. These topics are covered in great detail elsewhere [18,28–30] and are provided here to give those readers unfamiliar with nanoscale thermal transport context for the perspectives written as part of this work.
1.2.1 Thermal Transport Within Nanostructured Materials.
In solids, heat is carried predominantly by electrons (for metals) and/or phonons (for nonconducting materials). At device length scales proportional to the mean free path of these energy carriers, scattering elements like grain boundaries and point defects can profoundly reduce the thermal conductivity of a material, which then makes thermal abatement significantly more challenging for packaging engineers. Consequently, a fundamental understanding of energy carrier scattering is critical to the design of thermal management solutions for next-generation packaging systems.
where σ is the electrical conductivity of the material (S/m), kB,eV is the Boltzmann constant in electron volts, and T is the absolute temperature of the material (K). We note that the electronic structure and scattering in materials can result in the underprediction of κe when applying the Wiedemann–Franz law, but for most electrically conducting materials, the Wiedemann–Franz law provides accuracy to within –40% at noncryogenic temperatures [32–34]. Several mechanisms can contribute to electron scattering, including electron–electron and electron–phonon scattering . In the remainder of this work, we limit further discussion of nanoscale thermal transport to phononic contributions to thermal conductivity as the majority of our nanoscale constituents and interfaces include nonconducting materials.
Phonons are quantized lattice vibrations that are best thought of as a collective set of atomic oscillations about their equilibrium positions. The oscillations are governed by the atomic mass(es) of atoms, the strength of the bonds between neighboring atoms, and the material system geometry. Together, these material characteristics synchronize the modes of vibration, which are collectively termed “phonons.”
The phononic contribution to thermal conductivity can be quantitatively determined using a variety of analytical, numerical, and experimental techniques. Commonly used analytical techniques include solutions to the Boltzmann transport equation (BTE) [36,37] and augmentations to the well-known phonon gas model  (more on this below). Computational simulations can be performed using molecular dynamics (MD) simulations [39–42], density functional theory [43,44], and Monte Carlo ray tracing simulations [45,46]. Finally, nanoscale experimental techniques include electrothermal characterization (3-ω , transient electrothermal [48,49], and scanning-probe based [50–52] systems) and optical pump-probe thermoreflectance characterization (time-domain thermoreflectance (TDTR) [53–56], frequency-domain thermoreflectance [57–59], and steady-state thermoreflectance ).
In Eq. (2), Cv is the volumetric heat capacity of the solid (J/m3·K), ν is the phonon group velocity (or sound speed in a Debye approximation ) within the solid (m/s), and τ is the phonon scattering time (s). In Eq. (3), which assumes an isotropic, spherical Brillouin zone, ℏ is Planck's constant (J·s), ω is angular frequency (rad/s), is the temperature-dependent Bose–Einstein distribution, and k is wavevector (rad/m). Note that one must incorporate contributions from all polarization branches, j, to compute the total thermal conductivity, κ, and volumetric heat capacity, Cv.
There are several phonon scattering mechanisms that are particularly relevant to micro-electronic and power electronic-based material systems. These include phonon–phonon scattering (or so called “Umklapp” and “Normal” scattering), τph, baseline impurity scattering, τbulk, boundary scattering, τb and defect scattering, τd. Boundary scattering refers to phonons that collide and scatter off of a physical boundary, which could be the characteristic dimension of the system (i.e., the layer thickness) or inherent boundaries within the system (i.e., grain boundaries). Likewise, the defect scattering term represents both point defects and vacancies.
where A, B, and C are fitting constants. Provided these fitting constants, one can then determine the impact that characteristic length scales, material impurities, and crystalline microstructure have on thermal conductivity. We choose to demonstrate the magnitude that length scale has on thermal conductivity for three relevant materials: Si, GaN, and AlN. Using the phonon dispersion provided above each temperature-dependent thermal conductivity distribution in Fig. 5, we determine constants A, B, and C for each bulk material.
where τd represents the defect scattering parameter, ω is the angular frequency of the phonon modes (1/s), χd is the defect concentration, ΔMd is the difference in mass between the defect and the average host atom (Mh), ΔGd is the difference in shear strength between the defect and the average host atom (Gh), γ is the Grüneisen parameter, and Δδd is the difference between defect and average host atom radii (δh).
To vary the impact of characteristic length scale, the thermal conductivity of 100 nm to 1 mm-thick films of Si is determined using Eqs. (2) and (5) in tandem. Similarly, the concentration of defects (χd) is changed to demonstrate its impact on thermal conductivity. Both results are reported in Fig. 6.
Figure 6 clearly indicates that nanostructuring can have an extreme impact on the thermal properties of micro-electronics and power electronics-based materials. In this case, thin films of materials and material defects negatively impact (i.e., reduce) the thermal conductivity of the host material(s) and therefore increase the need for more aggressive thermal abatement strategies.
1.2.2 Thermal Transport Across Nanostructured Materials.
As with the thermal properties of the films themselves, thermal transport across thin-film interfaces can be impacted by nanosized features. Critically, even perfectly bonded interfaces experience a temperature drop due to a finite thermal boundary conductance . This is particularly important as device length scales are reduced and the interfaces between materials begin to contribute more significantly to the overall thermal resistance in the device stack, rendering it difficult to remove heat at the device level. In general, this is not always a detriment; one can deliberately scatter phonons by engineering interfaces, which has proven critical for the development of advanced, nanostructured thermoelectric materials [63,69,70].
The conventional analytical framework for determining the so called “thermal boundary conductance” (or hBD) across a bonded interface is predicated on whether energy carrier scattering occurs diffusely or is governed by acoustic reflections of phonons at a material junction. In particular, the diffuse mismatch model (DMM) and acoustic mismatch model (AMM) were developed to better understand heat flow across atomically smooth interfaces .
In Eqs. (8) and (9), ρ is material density, vl represents longitudinal sound speed and θ represents the incident polar angle for phonons that interact with (i.e., transmit or reflect across) an interface.
The AMM itself is typically reserved for computations of thermal boundary conductance at extremely low temperatures where the thermal phonon wavelengths are long relative to length scales of interfacial asperities (<7 K ).
A variety of works have been performed to assess the validity of the above model, with variations to the transmission coefficient made to account for a full density of states when necessary (for instance, when the elastic constants at an interface are highly anisotropic ). Here, we elucidate the representative magnitude of hBD on the overall thermal resistance of a multilayer system (where we compute the thermal resistance across the interface as Rth,int = 1/hBD) in the form of a temperature rise in Fig. 7 for GaN/diamond and GaN/Si. In these computations, we assume each layer is 5 μm thick and heat dissipation through the material system is q″ = 5 kW/cm2, consistent with future device-level thermal abatement requirements [77,78].
The thermal boundary conductances for each of the aforementioned interfaces are provided in Table 1 alongside experimentally determined values from literature.
|Interface||DMM hBD (MW/m2·K)||Experimental hBD (MW/m2·K)|
|Interface||DMM hBD (MW/m2·K)||Experimental hBD (MW/m2·K)|
DMM computations are compared to experimentally measured hBDs at similar material interfaces.
With little overlap in the phonon density of states (white region of overlap in the right-most plots in Fig. 7) between both GaN and diamond and GaN and Si, the hBD across the interface is expectedly low relative to other material combinations having greater overlap (such as Al/Si, which has a reported hBD of –208 MW/m2·K ). As a result, there is a large temperature difference across the interface shown in the left-most plot of Fig. 7. Note that we do not account for any grain gradient distribution in either the GaN or the diamond and instead assume a constant thermal conductivity through the thickness of each material. As will be discussed, however, many high-throughput growth techniques result in a grain gradient distribution that has significant impacts on thermal conduction through each material. Nevertheless, Fig. 7 demonstrates the importance of considering nanoscale interfacial thermal transport in electronics packaging material systems.
For the remainder of this work, the authors provide the reader with individual perspectives on the impacts of nanoscale thermal transport within and across relevant device features (such as those shown in Fig. 4). Each individual section is titled with individual author contributions, where each author in the paper has contributed a perspective (or series of perspectives) that reflect their area of expertise. The collection of contributing authors in this work was established with different elements of Fig. 4 in mind and within the specific context of nanoscale thermal transport.
2 Device-Level Nanoscale Thermal Transport
Mitigation of heat at the device and material level is critical to the successful development of next generation electronics devices. Substantial thermal challenges arise by: (a) the selection and growth of materials and (b) the interfaces between the active material and the other layers in the device. Perspectives on strategies to mitigate these challenges are presented in Secs. 2.1–2.3.
2.1 Wide Bandgap Materials for High Power Devices and Radio Frequency Electronics (Wilson).
The goals of electronic materials development have primarily been focused in two directions: faster switching speed (i.e., higher frequency) [82–84] and higher power [85–90]. In communications [82–84,91,92] and computational electronics [11,13–15], higher frequency is desirable, while higher power delivery is desired for electric vehicles [26,88,93], industrial and utilities [2,94,95], and military applications [96–98]. To move successfully in both directions, the industry must transition away from silicon, and to devices made from wide bandgap materials.
To that end, several materials have been researched to replace silicon as a semiconductor material. However, due to established procedures and architectures in place, and a lack of material that can be readily folded into existing manufacturing capabilities, silicon remains the material most widely used in semiconductor devices [88,90], despite several important limitations in key properties for performance. These include: maximum electric field strength before breakdown, maximum operating temperature, thermal conductivity, electron mobility, and bandgap [88,99]. Wide bandgap (WBG) materials (with bandgap greater than 1.5 eV) offer potentially viable alternatives to silicon. Viable alternatives include SiC, GaN-based devices, GaOx, and diamond-based devices. Performance metrics either substantially surpass or rival those of silicon in each case. Figure 8 depicts a comparison of properties of wide-bandgap materials proposed as alternatives to Si. Data found in Fig. 8 are from literature values at room temperature, reported in references [27,66,100–113].
For each WBG material, the benefits, drawbacks, and current outlook are summarized. Because SiC is a well-understood material, and devices using it are mature technology, currently in use in many commercial products with advantages over Si well-established, discussion on SiC as a WBG material is skipped. For more information on SiC as a WBG material, please read Ref. .
It can clearly be observed that diamond boasts advantage over silicon in every area in Fig. 8. Research has been heavily focused in this area, and recent demonstrations have shown that diamond can be made into an electronic material [43,66,102,104,114–121]. However, several substantial challenges with production, integration, doping, and contacts remain [114,115]. For many years, diamond was regarded as an excellent choice for passive thermal regulation, but because of high processing temperatures, it was doubtful that it would be useful as an active material . However, as recently as 2018, it has been shown that diamond can be made as a robust active material, with excellent electron and hole mobility . Terminating the diamond with hydrogen allows for a two-dimensional hole gas (2DHG) to form, significantly boosting maximum current (from –1 mA/mm to –100 mA ). However, it is difficult to control doping levels and device performance for both n-type and p-type diamond [94,116]. This may potentially be remedied by hybridizing WBG materials to achieve high-power, high-frequency devices [122,123].
Thermal conductivity is routinely touted as a superior characteristic of diamond, boasting a value of over 2000 Wm−1K−1 . However, in practice, diamond grown by chemical vapor deposition (CVD) or epitaxy is susceptible to significantly varying thermal properties in-plane versus cross-plane. While thermal conductivity is extremely high within a grain (–1800 Wm−1K−1 ), diamond grown by CVD tends to form a seed layer as the film begins growth. This leads to significant phonon scattering at the grain boundaries, reducing the thermal conductivity in the direction perpendicular to grain boundaries by nearly a factor of four (to –500 Wm−1K−1) . Also, due to expense, diamond is typically grown in thin-film form. Due to diamond's extremely large phonon mean free path, size effects play a significant role, even at high temperatures. Donovan and Warzoha theorize that 50 nm diamond films will have thermal conductivity less than 100 Wm−1K−1 . Thermal conductivity of doped diamond is also significantly reduced compared with pristine diamond; boron dopants with >1019 concentrations have been shown to lead to thermal conductivity values of only 700–1200 Wm−1K−1 at room temperature [126,127]. The literature is surprisingly sparse on thermal conductivity of doped diamond and hydrogen-terminated diamond, and this is a point of concern. Since diamond's ultrahigh thermal conductivity hinges on its large phonon mean free path, it is critical to characterize the effect of adding dopants or altering termination bonds on the thermal conductivity of diamond.
Overall, the outlook on diamond electronics is quite promising. Given the progress made in the field in very recent years, diamond is well-poised to emerge as the best option among WBG semiconductors to advance power and RF electronics.
Gallium oxide (-Ga2O3) has recently garnered significant attention as a WBG material, owing to its low cost, wide bandgap (4.7 eV), and advantageous electrical performance properties compared with other WBGs and especially silicon [128,129]. Compared with Si, SiC, and GaN, -Ga2O3 is projected to be much more efficient and have a much higher electric field break-down strength , and is thus potentially ideal for high-voltage applications.
However, -Ga2O3 has relatively low electron mobility (–4.67× lower than Si), and is therefore not well-suited for high-frequency applications. Perhaps the most substantial issue with -Ga2O3 is that it significantly lacks ability to conduct heat. Thermal conductivity in -Ga2O3 is highly anisotropic, and is significantly lower than other WBGs and Si (–27 Wm−1 K−1 in the (001) direction and –12 Wm−1 K−1 in the (100) direction) . Proponents of -Ga2O3 suggest that thermal conductivity matters less for -Ga2O3 than other WBG materials due to substantial enhancements in efficiency, temperature stability, and maximum temperature operation . However, devices will generate heat as they operate, and that heat will need to be dissipated, which -Ga2O3 is not well-equipped to do. Interestingly, -Ga2O3 shares many of the phonon scattering characteristics of GaN, which has around ten times larger thermal conductivity ; however, three-phonon scattering processes dominate in -Ga2O3, leading to a much shorter phonon relaxation time, which manifests as a significant reduction in thermal conductivity. To mitigate this issue, -Ga2O3 has been applied to higher thermal conductivity substrates (such as diamond) . However, the interface thermal resistance between -Ga2O3 and diamond, as well as between -Ga2O3 and metal, has been found to be quite large [132,133]. This is attributable to differences in the phonon density of states between -Ga2O3 and the other materials. Recently, it was demonstrated that by adding a carefully selected interlayer, thermal boundary conductance between metal and -Ga2O3 can be significantly enhanced, by more than 10× .
The outlook on -Ga2O3 is promising; however, thermal challenges will be a significant barrier to realization in a commercial device. The path to successful integration in high power electronics will be through thin layers of -Ga2O3 on interfaces that have been engineered to enhance phonon transport, thereby mitigating the deleterious effects of the poor thermal properties of the material itself.
GaN is exceedingly attractive for the manufacturer, especially for high voltage operation, and high switching frequencies. These devices are capable of operating at high voltage and high frequency by nature of the two-dimensional electron gas (2DEG) that is formed between the typical AlGaN layers deposited on GaN. This 2DEG forms due to spontaneous polarization of GaN, as well as a large discontinuity in the conduction band between the GaN and AlGaN layers. The properties of the 2DEG change significantly in the presence of electric fields. Electron mobility is extremely high for AlGaN/GaN heterostructures (>2000 cm2/(V·s)) . There are several other practical benefits to using AlGaN-based devices as well including current density , boost in switching frequency , etc. However, the early developers of these devices did not consider thermal properties (particularly thermal resistance added at heterogeneous material interfaces) among the most important concerns. Since bulk GaN has thermal conductivity comparable to Si, substrate thermal conductivity is a severely limiting factor. Because of this, GaN device layers are frequently removed from substrate and attached to substrates of higher thermal conductivity (or grown on substrates other than Si or sapphire) .
Recent studies have shown that the thermal boundary resistance at heterogeneous material interfaces (especially between active material and substrate) may account for a substantial portion of the overall device thermal resistance [136–139]. Graham et al. have reported values recorded by them and others [137,140–142] of GaN-based devices on various substrates and found that although substrate thermal conductivity may be vastly improved by replacing Si with SiC or diamond, interface thermal resistance may take a hit (going from a record low of 1.5–2 m2K/GW for GaN on Si to –10 to 100 m2K/GW for GaN on diamond [115,119,143]).
Although much attention has been given to the interface between GaN and the substrate, very little attention has gone into investigating the thermal resistance that occurs between the active layers in the device and the metallization, or even the interface between AlGaN and GaN, where the 2DEG forms. Several recent studies have proposed methodologies for probing the peak device temperature, using a combination of thermoreflectance and Raman temperature measurement techniques [144,145]. In conjunction with multiscale finite element and molecular dynamics models, accurate determination of the peak temperature rise in the devices for a given measured temperature rise at the surface or of the volume may be inferred [144,146]. However, owing to the interfaces that are necessary to make a device with AlGaN on GaN, the overall thermal resistance of the devices increases, leading to peak temperature rise of up to 42% over the case where the interface is perfectly thermally conductive.
Figure 9 depicts this, based on a combination of 3DFE simulations from a phonon hydrodynamic model, and experimental measurements of the AlGaN/GaN interface via frequency-domain thermoreflectance . Therefore, in power electronics, material properties as well as properties of material interfaces are critically important to the development of better devices. Thermal resistance in multilayered structures leads to significant build-up of peak temperature, while bulk thermal conductivity is the limiting factor when using substrates with lower thermal conductivity. In both cases, processing conditions, functionalization, and careful selection of interstitial layers will allow for optimal thermal performance of wide-bandgap devices to be used in power and RF electronic devices.
2.2 Nanoscopic Heat Flow Constriction in Wide Bandgap Electronics (Choi).
5G wireless networks offer significant advantages over the current 4 G technology, including higher speed and lower latency, suitable for serving as the backbone of the Internet of Things (IoT), connecting more than a trillion devices to the Internet. However, in order to compensate for the increased energy and range demands arising from the network growth, significant improvement in the energy efficiency of base stations is necessary. Approximately 60% of the total power consumption of base stations is attributed to the loss associated with RF power amplifiers .
Gallium nitride (GaN)-based RF power amplifiers, that feature broadband operation and high efficiency, are key components to realize 5 G network base stations and small cell applications including mobile devices [82,84]. However, the last piece of the puzzle to enable GaN for 5 G is to overcome thermal reliability concerns stemming from localized extreme temperature gradients beyond predictions based on macroscale heat transfer principles such as Fourier's law of heat conduction.
Figures 10(a) and 10(b) show the structure of a GaN-based high electron mobility transistor (HEMT) [89,150–154]. To construct the device, a 1–4 μm thick GaN layer is heteroepitaxially grown on a nonnative substrate where the common choices are silicon (Si) and silicon carbide (SiC) substrates. Subsequently, a thin (–20 nm) aluminum gallium nitride (AlGaN) layer is pseudo-morphically grown over GaN. A physical effect that governs the device behavior is the formation of a two-dimensional electron gas (2DEG) , which serves as the current channel. The 2DEG is an electron aggregate that is free to move in two dimensions (x- and y-directions in Fig. 10), but tightly confined in the third dimension (z-direction). Accumulation of the high density 2DEG without impurity doping is due to the formation of a deep spike-shaped quantum well at the AlGaN/GaN heterointerface, where there is a large conduction-band offset (Fig. 10(c)). A vast amount of electrons are drawn into the quantum well due to the large piezoelectric polarization induced via tensile strain built in the AlGaN layer (Fig. 10(d)). This translates into a large current-carrying capability between the drain and source electrodes compared to conventional devices [149,155]. The current level can be modulated (reduced) by applying a negative gate voltage to partially deplete the 2DEG channel. The wide band gap (EG = 3.4 eV) of GaN results in a breakdown field of –3 MV/cm, which is an order of magnitude larger than that for conventional materials that have been used to build RF power amplifiers. This enables higher voltage operation with a smaller device footprint.
The power amplifier's role is, as the name suggests, to convert a small input signal (e.g., the gate voltage of a transistor) into a much larger power (current × voltage between the drain and source electrodes) to be delivered to the load. Therefore, GaN HEMTs, when employed as RF power amplifiers, offer high power density (=currentvoltage/active area), power-added efficiency, gain and ease in impedance-matching that significantly improves the overall efficiency in the RF chain. Moreover, the ability of GaN transistors to work in the high-frequency range gives promise for them to evolve from 5 G base stations to small cell applications and, potentially into mobile devices.
However, this substantial improvement in size, weight, and power translates into extreme power densities (>50 kW/cm2) in the active region of GaN HEMTs as shown in Fig. 11 [92,156]. Thermal failure (Fig. 11(b)) and reduced component lifetime [157,158] caused by device self-heating are major roadblocks to the successful implementation of GaN technology into 5G network components. Intense channel temperature rise caused by high voltage and power operation  was shown to trigger and aggravate various degradation mechanisms [160–164]. Such failure mechanisms include mechanical damage in the AlGaN barrier due to induction of thermo-elastic stress  and thermally assisted interdiffusion at the semiconductor/metal interface . Although GaN HEMTs have been commercialized for small-scale applications (e.g., laptop chargers), questions regarding GaN device thermal reliability remain unanswered [166,167], as evidenced by the continued research into their life expectancies [157,168,169].
The industry-standard method to estimate GaN HEMT lifetime is the temperature-accelerated direct current operational-life test . The Arrhenius extrapolations reported in the literature [157,169] show extremely long predicted median times that significantly overpredict the actual device lifetime in field applications. This is a major concern in industry because such false prediction may lead to catastrophic events in reliability critical applications [157,168,169]. The overprediction of device lifetime stems from inaccurate estimation of the device peak temperature at the site of degradation/failure during the accelerated high power testing. It was shown that an error of only 2 °C in the estimation of device peak temperature used in the temperature-accelerated life test can skew the predicted lifetime by a factor of two [166,167].
Currently, industrial practices for device thermal analysis and accelerated direct current operational life tests [157,169] rely on simulation data based on the simple and widely accepted Fourier's law of heat conduction. However, a limited number of pioneering theoretical studies [170–174] have suggested that a nanoscale temperature spike or a so-called hot-spot forms in GaN HEMTs, which can be significantly hotter than predictions based on purely diffusive thermal transport models (i.e., the Fourier's law of heat conduction). This unanswered question has inhibited the use of GaN devices for high power RF applications where demonstrated long product lifetimes are required [158,175].
In practice, large voltages are applied between the drain and source (e.g., VDS = 28–48 V) of GaN RF power amplifiers to reduce or eliminate the need for step-down voltage conversion to match the operating voltage of commercial systems (e.g., wireless base station) . In addition, the wide bandgap of the material allows the use of considerably shorter channel lengths (several microns) than conventional devices. This results in considerable electric field concentration within the 2DEG channel underneath the drain side corner of the gate .
Figure 12 shows heat generation profiles of a GaN HEMT under two different bias conditions resulting in an identical total power dissipation (e.g., PDISS = VDS × IDS = 500 mW; PDISS, VDS, and IDS stand for dissipated power, drain-source voltage, and drain-source current, respectively). Figure 12(a) shows the Joule heating is highly concentrated beneath the drain end of the gate for high voltage-low current conditions (e.g., VDS = 50 V, VGS = −1 V, IDS = 10 mA). On the other hand, Fig. 12(b) shows that a relatively uniform Joule heating distribution occurs for low voltage-high current conditions (e.g., VDS = 5 V, VGS = 2.5 V, IDS = 100 mA). For low voltage-high current conditions, the lower VDS produces the same amount of power dissipation (500 mW) since the channel is fully open (manifested by a large IDS). The 2DEG current flow is not constricted, causing the heat generation profile to be relatively uniform across the entire channel. In contrast, for high voltage-low current conditions, to accomplish an identical power dissipation, IDS is restricted by applying a negative voltage on the gate (VGS), thereby forming a local depletion region that partially pinches off the channel. This local depletion region with high electrical resistance causes spatial confinement of the 2DEG Joule heating. This leads to formation of a nanoscale hotspot [170,172–174] subject to extreme local heat flux (>1 MW/cm2). According to fully coupled electrothermal simulation [158,175,178] shown in Fig. 12(a), the domain size of the peak heat generation zone can be less than 10 nm × 50 nm, which is in agreement with theoretical predictions in literature [172,179].
where Λ is the phonon mean free path, T is the temperature, c is the volumetric heat capacity per unit phonon mean free path, v is the phonon group velocity, and s indexes the phonon polarizations (i.e., different vibrational modes). Since the integral is defined from 0 to Λ*, kaccum quantifies the contribution of phonons with a mean free path less than Λ* to the overall bulk thermal conductivity.
The thermal conductivity accumulation function of GaN  indicates that phonons with Λ less than 550 nm and 1000 nm contribute to –50% of the bulk thermal conductivity of GaN at T = 415 K and 309 K, respectively. At higher temperatures, the larger phonon population results in more frequent phonon–phonon scattering events, which reduce the effective mean free path of the principal heat carriers (i.e., phonons).
Under high voltage-low current operation (Fig. 12(a)), because of the extreme heat source size reduction, heating would take place primarily over length scales less than the mean free path of phonons tasked with energy delivery. As mentioned above, phonons with mean free paths greater than –550 nm are responsible for more than 50% of the thermal conduction in the GaN lattice at –400 K [182,183]. Therefore, within the nanoscale heat source domain (<50 nm), the opportunity to effectively transport energy away via phonons with longer mean free paths (>550 nm) is lost, i.e., the onset of ballistic transport occurs. Thus, this nanoscopic “heat source size effect” will restrict thermal transport from the device hot-spot causing a net increase in channel temperature beyond predictions based on Fourier's law.
This study  has investigated the self-heating behavior of a GaN HEMT fabricated on a Si substrate operating under high VDS-low IDS conditions that are expected to cause non-Fourier thermal transport. A near-ultraviolet (UV) thermoreflectance imaging technique and a coupled 3D electrothermal model  that accounts for ballistic-diffusive thermal transport effects were used to study amplified heating beyond predictions solely based on the Fourier's law of heat conduction.
Temperature measurement of the device channel was performed using a near-UV illumination source with a center wavelength of 365 nm. Results are shown in Fig. 13(a). The diffraction limited lateral spatial resolution was 300 nm. Since absorption is strong near the GaN surface for near-UV illumination, the measured temperature was weighted toward the 2DEG channel region, within –55 nm [185–189] from the GaN surface. The coupled electrothermal modeling scheme was similar to that in Refs.  , and  but was extended to three dimensions. This device model was developed to validate the near-UV thermoreflectance results. The coupled modeling scheme self-consistently solved, for each mesh point, the Poisson, current continuity, and electrohydrodynamic equations (for electronic transport), and the BTE [170,172] (for thermal transport) to derive the electrostatic potential, electron/hole concentration and their energy/temperature distributions, heat generation, and electron/hole/lattice temperature rise. Consequently, the model accounted for the nanoscopic heat source size effect.
Channel peak temperatures were deduced from experiments and modeling for multiple bias conditions. Results are displayed in Fig. 13(b). Measurement, Fourier-, and BTE-based simulation shown excellent agreement for low to moderate VDS bias conditions for all tested power dissipation levels. In stark contrast, a large disagreement (>10%) in channel peak temperatures between the Fourier and BTE simulation results was observed for high VDS conditions, for all tested power dissipation levels (Fig. 13(b)). Moreover, experimental values shown excellent agreement with the simulated temperature profiles from the BTE gray model reflecting the mean free path spectra of GaN acoustic phonons [170,183,190–193]. Results of this study clearly suggest that non-Fourier thermal transport mechanisms are in play, leading to the observed amplified heating. Many laser-based pump-probe experiments [181,194–200] support this experimental study. They have demonstrated that under conditions where the heat source domain size is less than the mean free path of dominant heat carriers, the heat source region exhibits a local reduction of the effective thermal conductivity compared to the bulk value.
2.3 Gallium Oxide: A Promising Ultra-Wide Bandgap Material (Donmezer).
A new and exciting group of materials emerging within the electronics community is the ultrawide bandgap (UWBG) materials. These materials, such as AlN, diamond, cubic boron nitride (BN), and Ga2O3 (with bandgaps that exceed 3.4 eV), have the potential for superior performance relative to conventional and wide band-gap materials such as GaAs and GaN. Devices fabricated from these materials are still immature due to a variety of fabrication challenges and material performance limitations. The absence of readily available large-area, low-defect density, single-crystal substrates, and doping control issues remain fabrication challenges for the commercialization of AlGaN/AlN and diamond-based electronic devices. Despite these problems, researchers fabricated functioning electronic devices such as diamond  and AlN/AlGaN field effect transistors [202–204] as shown in Fig. 14.
Among all UWBG materials, β-Ga2O3 is the most promising one since low-cost and large substrates are available for its growth . β-Ga2O3 power devices are poised to reach the commercial sector with performance rivaling or surpassing that of GaN and SiC devices at much lower cost.
Although not investigated in detail, thermal problems observed in high-power devices are also present. Similar to AlGaN/GaN HEMT transistors and Si metal oxide semiconductor field effect transistors (MOSFETs), these devices experience reliability issues associated with localized heating in their active areas. Thermal transport from the active areas is controlled by the thermal conductivity of each material and the thermal boundary conductance (hBD) between individual material layers. Epitaxial material layers can have thicknesses varying between tens of nm (as in Fig. 14) to a few μm. Thus, they often have thermal conductivities smaller than their bulk counterparts due to thin film size effects. Diamond, which has a much larger bulk thermal conductivity than most other substrates due to longer phonon mean free paths, suffers as a result of these size effects to an even greater extent. Alloy semiconductor layers such as AlGaN with low thermal conductivity due to additional phonon scattering events caused by the alloy particles also requires special attention. hBD between material layers caused by the significant lattice mismatch can also play a significant role in heat transfer.
To design better performing devices, accurate thin film thermal conductivities and hBDs obtained via experimental and/or theoretical approaches should be used for thermal characterization studies. Bulk β-Ga2O3 has low thermal conductivity (k = 15 W/m·K) and is doped in most of its functioning devices. Moreover, its thickness is often in the range of hundreds of nanometers. These factors may lead to further reduction in thermal conductivity in accordance with the physics presented in Sec. 1.2. In the past, thermal conductivities of doped and undoped bulk and thin film β-Ga2O3 samples were measured at different temperatures using techniques such as 3ω and TDTR [206–208]. Thermal conductivities of 300–1000 nm thick AlN thin films obtained using 3ω technique are measured to be between k = 5.4–17.7 W/m·K . Moreover, phonon thermal conductivity—mean free path spectra of UWBG materials obtained through experimental and theoretical approaches can be used the predict size dependence of thermal conductivity [181,210]. Finally, the hBDs between β-Ga2O3/diamond , i-Ga2O3/metal , and AlN/AlGaN  interfaces have been obtained using a variety of experimental and theoretical approaches. These findings generally show that the already low thermal conductivity of UWBG materials is further reduced in their thin film form; when combined with the low hBD between these materials and their substrates, a thermal bottleneck can form and result in inadequate heat dissipation. Consequently, the impacts that nanosized features have on thermal transport within the device and at its boundaries should be considered carefully in device analysis.
With the help of accurate thermal conductivities and hBDs, thermal characterization of devices can be performed through simulations to analyze device temperatures and provide relevant metrics for thermal solutions. Past attempts have used anisotropic thermal conductivities of Ga2O3 (though ignored the impact of potentially high hBDs) to analyze MOSFET and MESFETs through electrothermal simulations [212–214]. Although this remains an area under active investigation, results from previous studies highlight the importance of nonuniform Joule heating distribution and its effects on temperature, as shown in Fig. 15. Nonuniform heating distribution is also observed near Schottky junction of β-Ga2O3 diodes , in MOSFETs with hexagonal boron-nitride (h-BN) gate insulators , and expected in vertical FinFETs .
where is the integrated energy density found by integrating the phonon energies along all frequencies and polarizations, is the volumetric heat generation term that represents the Joule heating of the device, is the relaxation time, is the phonon group velocity, and is a unit vector pointing in the direction of the phonon group velocity .
Therefore, Joule heating distribution, ballistic-diffusive heat transport near hotspots, thin film thermal conductivities, and hBD values should all be considered for accurate device simulations, and highlights the importance of nanoscale energy transport considerations for thermal management of high-power electronic devices. Additionally, accurate representations of the device geometry and its peripheral components with an appropriate 3D model and the proper selection of thermal boundary conditions is critical to understanding such impacts on device performance. Therefore, the development of multiphysics and multiscale simulation techniques with reasonable computational cost is crucial for the development of next-generation UWBG devices.
3 Nanoscale Energy Transport Across Bonded Interfaces
The performance of high power electronics, thermoelectrics, phase change memory, and logic circuits is frequently limited by the thermal boundary resistance (Rth) at interfaces of devices [219,220]. These interfaces are designed to optimize the electrical performances without considering thermal management at the same time. As characteristic length- and time-scales become comparable to the mean-free-paths and lifetimes of energy carriers in materials and devices, thermal resistance associated with interfaces between solids can become a major impediment and may lead to thermal breakdown of devices if heat cannot be dissipated efficiently . Rth is sometimes comparable to (or even larger than) the thermal resistance of materials, thus contributing significantly to the overall resistance of the whole device. Therefore, increasing thermal boundary conductance (hBD = 1/Rth) is necessary in order to maintain reasonable device temperature to avoid thermal breakdown.
For typical crystalline interfaces where heat transfer is primarily driven by lattice vibrations, typical values of measured hBD are in the range of –20 to 300 MW/m2·K (Rth ≈ 3.3 × 10−9 to 50 × 10−9 m2·K/W). In addition to the fundamental properties of the energy carriers in the two solids, interfacial resistance also depends on a variety of other factors such as temperature, interfacial disorder, roughness and dislocations at the interface, and weak interfacial bonding. Experimental and simulation approaches to further understand these effects at interfaces are presented in Secs. 3.1–3.3.
3.1 Nanoscale Interfaces (Giri, Hopkins).
The understanding of the various factors dictating hBD has been greatly facilitated by recent advancements in experimental metrologies used to measure hBD across buried interfaces or interfaces comprising 2D material systems and computational advances in atomistic simulations that can mimic realistic interfaces. For example, it has been shown that interfaces formed with an amorphous solid can have very high interfacial conductances (Fig. 16), which is counterintuitive to the conventional wisdom that disorder usually enhances thermal resistance [222,223]. Likewise, electron-dominated thermal transport across interfaces (usually between two metals in contact, with interfacial thermal conductance typically of the order of 1 GW/m2K) has been shown to possess more than an order of magnitude higher conductances than typical phonon-dominated heat flow (of the order of 100 MW/m2K) across interfaces [224–226]. Moreover, epitaxial interfaces formed between materials with similar lattice constants and high quality of interfaces have also been shown to demonstrate high conductances (hBD > 500 MW/m2·K) [227–229].On the contrary, extremely low conductances have been measured for materials with highly dissimilar vibrational density of states and large mismatch in their elastic constants such as bismuth deposited on diamond substrates with reported hBD of 8 MW/m2·K. To put things into perspective and highlight the disparity in the measured hBD, the resistance of bismuth/diamond interface is greater than that of a 100 nm thick amorphous SiO2 layer, whereas the resistance measured for a TiN/MgO epitaxial interface is comparable to that of a 1 nm thick amorphous SiO2 layer.
Extrinsic factors such as pressure and nanostructuring through interfacial mixing, roughing with nonplanar structures, and chemical functionalization has been shown to control and enhance hBD in a wide range across various types of interfaces [230–241]. For example, Losego et al.  experimentally demonstrated that interfaces formed with weak van der Waals interactions can be converted to covalent bonding via self-assembled monolayers (SAMs) between Au and quartz, leading to an increase in hBD by as much as 80%. Similarly, increase in the overall contact area by patterning nonplanar features of nanofabricated fin-like projections at metal/dielectric interfaces can substantially increase the measured hBD [230,231]. Stiffening the bonds at the interface via mechanical strain (performed with diamond load cells) has also been experimentally shown to be an effective way to enhance hBD [119,242]. These strategies for enhancement in thermal conductance are summarized in Fig. 17.
Along with the experimental advances, atomistic simulations based on MD simulations have led to tremendous progress in understanding the mode- and spectral-level contributions to interfacial thermal conductance between materials [23,118,243–249]. Some of these works have highlighted the importance of considering localized and nondispersive interfacial modes to accurately describe hBD, which are ignored while treating hBD with the typical formalisms based on the phonon gas models such as the DMM and AMM as discussed above. Furthermore, the assumption of elastic scattering in the aforementioned models that hinder their applicability to realistic material interfaces at room temperature and elevated temperatures is avoided in MD simulations that inherently account for elastic as well as inelastic pathways of heat transfer due to multiple phonon interactions that can play a significant role in dictating interfacial heat transfer across solids.
The failure of the phonon gas models has also been exemplified by comparing their predictions with experimental measurements of hBD on high crystalline quality nonmetallic solids as carried out in Ref.  for epitaxially grown ZnO/GaN interface (Fig. 18). This work directly highlights the inapplicability of the Landauer/transmission formalism-based theories by showing that the measured value of hBD = 490 MW/m2·K for ZnO/GaN is nearly a factor of 2 greater than the values predicted by these theories at elevated temperatures of –200 K and above. The disagreement points to the fact that the harmonic approximation adopted in the models could be incorrect and anharmonic channels of energy transfer could contribute to the enhancement of hBD as the temperature is increased. Anharmonic channels with multiple phonon scattering events affecting the transmission of vibrational energy across interfaces can lead to an increase in hBD by opening additional channels for interfacial heat flow [245,250–255].
3.2 Effect of Constituent Diffusion (Tian).
Interface roughness due to constituent diffusion commonly occurs at material interfaces . Atomistic Green's function (AGF) is a powerful tool to study thermal transport across interfaces.
Unlike the widely used AMM and DMM, which only consider the material properties on both sides, AGF includes the details of the microscopic structures at the interface (as depicted in Fig. 19). Using AGF, Tian et al.  studied the effect of constituent diffusion on hBD in the harmonic limit. To mimic the atomic diffusion, they created the atomic distribution at the interface to obey the half-Gaussian distribution. They found that the phonon transmission (and hence, hBD) is significantly enhanced by atomic diffusion compared to a smooth interface , which was contrary to the conventional notion at that time (Fig. 20).
They attributed this enhancement to the effect of bridging phonon density of states of bulk leads by the mixed region. In brief, atomistic diffusion can increase phonon transmission across two dissimilar materials if the diffusion length is properly controlled. It shares the same essence with later studies on enhanced thermal interface conductance by nanopillar arrays and adding a layer of impedance matcher at interface  (Table 2).
|Enhancement mechanism||hBD,low (MW/m2·K)||hBD,enhanced (MW/m2·K)|
|Nanopillar arrays||230 (at 300 K)||438 (at 300 K)|
|Interlayer ||1012.9 (at 30 K)||1251.7 (at 30 K)|
|Interface roughening ||210 (at 300 K)||277 (at 300 K)|
3.3 Enhancement of Thermal Transport Across Power Electronics Interfaces (Shi and Graham).
To enhance the thermal transport at interfaces, we first need to understand the mechanisms leading to thermal resistance at the interface. However, there are plenty of factors which can affect the hBD and Rth across interfaces , such as inelastic phonon scattering [246,259], interface disorder , different bonding strength [240,261], crystal orientation [121,262,263], and electron-phonon coupling [264,265]. Experiments and simulations are usually applied to study the contributions to thermal transport at interfaces of different mechanisms. For experiments, the TDTR method is one of the widest used and reliable methods to measure hBD [28,56,266]. For simulations, people usually use MD or Landauer formula with transmission functions from AMM, DMM, AGF, or phonon wave-packet method [71,257,267–273]. Within the framework of MD methods, nonequilibrium MD (NEMD) [274–276] and interface conductance modal analysis [115,143,277–283] are usually applied to predict hBD. The advantages of MD are that the anharmonic phonon scattering is included from the higher-order force constants of empirical interatomic potentials, and the interface structures are quite flexible, that complex interfacial details (like strong interfacial disorder and interfaces with dimensional mismatch) can be simulated. However, MD is computationally expensive and does not consider quantum effects, which will lead to inaccuracy at low temperature or small dimension. Also, MD relies on interatomic potentials and cannot be applied to systems without appropriate potentials. The advantage of Landauer approach is the consideration of quantum phonon statistics, which is important at sub-Debye temperatures. Moreover, for Landauer method with transmission functions from AMM, DMM, or AGF, phonon properties can be obtained from first-principle calculations, which means that interatomic potentials are not necessary, and for Landauer with AMM or DMM, the computational costs are not high. However, it is very difficult to include anharmonicity in Landauer approach, and the consideration of detailed interface structure or interface bonding strength in AMM or DMM is very hard to implement. Recently, there are several studies of considering anharmonicity in AGF [270,279], but there are still some limitations like high computational costs and inaccuracy from estimated scattering rate at interfaces.
At interfaces between two crystalline materials, because of the growth limitation, the crystalline quality of one or both of the materials near the interface is usually not very good or the interfacial bonding is not very strong from different growing methods, like evaporation , CVD [115,280], and atomic layer deposition [281,284]. The low-quality polycrystalline or even amorphous region near the interface will have reduced thermal conductivity compared to bulk crystal and will contribute an additional thermal resistance, and that thermal resistance might impede the thermal transport from devices, especially for high frequency applications. In a recent study of Al/sapphire interface with TDTR and Landauer approach with transmission from AGF and DMM, it is found that an ultraclean and atomically smooth interface can be obtained by growth via molecular beam epitaxy (MBE) . There are several reasons that the MBE Al/sapphire interface is ultraclean: the good quality of sapphire substrate, there is no reaction between sapphire and Al during growth, and the orientation of sapphire is carefully selected to ensure small lattice mismatch and similar crystalline structure. It is observed that the hBD at the MBE-grown Al/sapphire interface is larger than all other hBD measurements in literature . It is also observed that at the ultraclean Al/sapphire interface, the elastic phonon scattering dominates the phonon transmission, while inelastic scattering and electron–phonon coupling are not important.
From previous studies, some strategies to enhance the thermal transport at interfaces have been developed, such as lighter atom substitution , patterned interface , and room-temperature surface-activated bonding (SAB) technique [143,283]. From a study of hBD at SiC/GaN with NEMD method, it is found that substituting Ga atoms in the GaN lattice with lighter atoms near the interface can increase the hBD by up to 50% . From a study at Si/diamond interface with TDTR, NEMD, and Landauer formalism, it is observed that it is possible to increase the hBD at semiconductor dielectric interfaces by graphoepitaxially growing diamond on nanopatterned silicon wafers. Because of the importance of thermal transport at both semiconductor–semiconductor and semiconductor–dielectric interfaces in power electronic devices, there are studies attempting to directly bond crystalline semiconductor and dielectric materials together. If two single-crystalline materials could be directly bonded together, the material quality near the interface should be better than directly growing one material on another, and a high thermal conductivity dielectric material or semiconducting material (e.g., diamond) can be used as heat spreading material to enhance heat dissipation in the device. Although very high values of hBD are realized via MBE deposition, the growth is very slow and the process is difficult to scale in an industrial setting [143,283]. On the other hand, if two materials are bonded at high temperature, there will be residual stress at the interface because of different thermal expansion coefficients of two materials. The stress will affect interface quality and introduce additional thermal resistance [143,283]. Therefore, a room-temperature SAB technique is developed to achieve the high-quality interface of MBE with the manufacturing ease of material bonding. From the TDTR measurements, the measured hBDs at both GaN/SiC and GaN/diamond room-temperature SAB interfaces are among the high values reported in the literatures. Figure 21 reports the results of this study.
4 Nanoscale Heat Conduction in Two-Dimensional Materials (Donmezer)
Two-dimensional materials have drawn the attention of the electronics community over the last decade. Among them, graphene has been the most researched material due to its superior physical properties, such as high thermal conductivity (≈2000–5000 W/m·K)  and electron mobility . Graphene has been used in modern electronics applications such as flexible organic light emitting diodes , field effect transistors , and as heat spreaders . To open an energy gap in graphene and achieve functionality, various techniques such as chemical functionalization, quantum confinement (in nanoribbons), and electric field application (to bilayer and trilayer structures)  have been developed. Single layer h-BN that shares similar lattice parameters  with graphene is also a good candidate for electronic applications, due to its favorable properties such as high thermal/chemical stability and dielectric nature . Yet monolayer h-BN has a much lower thermal conductivity (≈500 W/m·K) compared to that of graphene .
Alongside the advancements in graphene and h-BN world, new functional 2D materials (2DMs) have also emerged. These materials, such as TMDs (transition metal dichalcogenides)  and phosphorene, have superior semiconductor performances due to their diverse, tunable electronic structures  and large bandgaps. In a very short period of time, the use of these materials in electronic and optoelectronic applications such as field effect transistors (FETs) and infrared detectors has been demonstrated. Emerging 2DMs also opened new horizons in the transistor community right when the physical limitations (i.e., source-drain tunneling below 5 nm) of Moore's law started to reveal themselves . Today, industries' interests in continuing gate length scaling have begun to diminish since there is increasing demand for logic and memory chips with low power consumption, e.g., for mobile applications. It has been proven that ultrathin channels provide improved electrostatic gate control and reduced short-channel effects, which results in better geometric scaling and less power consumption . To achieve this, 2DMs are considered as future channel materials for next-generation transistors. Among the future channel materials, MoS2, a type of TMD, has been investigated more than others due to its geological availability, environmental stability (even when present in monolayer form), as well as its conformity to low resistance contacts for electron injection .
Understanding heat transport mechanisms in emerging devices with 2DMs (whether used as channel materials or heat spreaders) is crucial for understanding and improving device reliability. Since heat dissipation in devices is significantly affected by the thermal conductivity of the materials close to the active regions and hBD between material layers, the first group of studies focused on this. Researchers found that both monolayer h-BN  and graphene [297–299] exhibit higher thermal conductivities than that of the corresponding bulk structures due to a reduction in phonon–phonon scattering events. Thermal conductivity of monolayer MoS2, which is lower than the bulk thermal conductivity of MoS2,  has been investigated through simulations and experiments, as well. Ab-initio simulations calculated the thermal conductivity of 1 μm sized suspended monolayers of MoS2 (83 W/m·K) at room temperature . Molecular dynamics simulations predict a much smaller in-plane thermal conductivity for MoS2 (1.35 W/m·K), three orders of magnitude lower than that of graphene, which is due to additional phonon scattering events caused by the sample size . Experimental results obtained using the Raman technique agree with the former also prove that lateral sample size, temperature, and the presence of isotopes, imperfections, and/or defects strongly effect the in-plane thermal conductivity of MoS2 monolayers [300,303]. Phonon thermal conductivity mean free path accumulation information obtained through theoretical calculations 2DMs  can be used to understand the changes in in-plane thermal conductivity of materials due to boundary scattering events in devices with small lateral dimensions.
In the majority of the above studies, investigated 2DMs were in suspended form. Yet, it is known that in real applications, these layers are often in contact with substrate and/or other material layers. Thus, not only the thermal conductivities of material layers should be investigated in the presence of other layers in close vicinity but also the hBD between material layers should be studied. A previous study measuring the thermal conductivity of supported MoS2 films on SiO2/Si substrates using Raman spectroscopy proves the strong dependence of thermal conductivity on temperature [303,304]. There are studies calculating the thermal conductivity of monolayer MoS2/MoSe2  and h-BN/graphene  heterostructures, which have potential use for electronic applications, using classical molecular dynamics and ab initio simulations, respectively. Finally, hBD between monolayer MOS2 and graphene grown on SiO2/Si substrates are obtained by analyzing the electrical thermometry results with 3D finite element analysis and are found to be 20.3-33.5 MW/m2K, much larger than the ones predicted by earlier Raman-based measurements . A more recent study using a similar Raman based approach obtains a hBD between MoS2 and SiO2 and AlN substrates as 15 MW/m2K, with reasonable agreement to latter study given the uncertainty of experiments . It is expected that both the low in-plane thermal conductivity of MoS2 and the hBD values of 2DMs in these ranges will limit energy dissipation from device active layers.
To understand the effect of these thermal properties on device temperature distribution and electrical performance, temperature characterization studies should also be performed. Past modeling efforts for device thermal characterization include ab initio modeling studies  and multiscale modeling studies where active areas in which nanoscale heat transfer effects are modeled through molecular dynamics simulations and the rest of the device being modeled through 3D finite element simulations . There are also studies modeling the entire 2D field-effect transistor (FET) structure by solving a quasi-ballistic heat transfer of phonons [310,311]. Temperature characterization can also be performed experimentally using high-resolution thermography techniques. For example, previously temperature distribution of the monolayer MoS2 transistors is obtained using Raman thermometry with –0.3 μm spatial resolution determined by the laser spot size . These studies show that thermal breakdown of such devices occurs at the drain side of the channel where highest temperatures are observed.
The results of previous studies reveal the importance of thermal analysis in improvement of the 2D electronic devices. To perform accurate thermal analysis studies and suggest thermal solutions for devices, correct use of thermophysical properties for the active areas of the devices, multiphysics/multiscale thermal modeling techniques, and high-resolution thermography techniques are required.
5 Two-Dimensional Material Interfaces (Giri and Hopkins)
As incorporation of 2D materials in devices such as in photovoltaics and field-effect tunneling transistors becomes ubiquitous [312,313], it becomes highly imperative to study the thermal conductance across 2D/3D material systems. In this regard, experimental methods such as Raman spectroscopy [307,314–316], pump-probe thermoreflectance [317–319], 3 technique [320,321], and electrical thermometries [306,322] have been utilized to measure the thermal conductance across interfaces comprising 2D materials. A large proportion of these studies have measured very low thermal boundary conductances in the range of 20–35 MWm−2K−1 across graphene on SiO2 and AlN substrates [306,318,319,323,324]. Moreover, Freedy et al.  have shown that one needs to be careful when describing heat flow across graphene interfaces since the thermal resistance across Ti/Gr/SiO2 contacts is largely dependent on the oxide composition at the contacts.
Both atomistic simulations [326–329] and analytical frameworks have ascribed the low conductances associated with 2D material interfaces to the coupling between flexural acoustic phonons of the 2D material and the substrate [76,259,330–334]. Along with the importance of flexural modes, Foss et al.  highlighted the role of the substrate properties such as sound speed and the mass density to be important factors while considering the heat transfer across 2D/3D interfaces.
6 Thermal Interface Materials and Nanoscale Heat Flow
Heat flow across thermal interface materials (TIMs) is fast becoming the largest source of thermal resistance in conventional electronics packaging systems [28,29,115,219,335]. This is principally due to: (1) improvements in the thermal properties of electronic materials and (2) reductions in the size of heat spreading components and heat sinks. In this section, we highlight recent advancements made in (and corresponding measurements of) thermal transport across TIM junctions via nanostructuring.
6.1 Nanoparticle-Based Thermal Interface Materials (Warzoha).
A variety of works have proposed the inclusion of nanoparticles in conventional TIMs to improve their thermal conductivity [336–338]. However, the disordered nature of nanoparticles often results in significant thermal contact resistance between adjacent nanoparticles  or between the nanoparticles and the surrounding matrix material [340,341]. As a result, it is often difficult to achieve theoretical improvements using effective medium approximations.
To reduce disorder, several studies have proposed the use of aligned nanostructures [342–344] having high thermal conductivity. These structures are often found to provide higher thermal conductivity than randomly dispersed nanoparticle-laden materials, but still suffer from poor thermal contact at relevant packaging interfaces and therefore do little to mitigate the large temperature drops that occur across interfaces.
In Eq. (14), RT is the total thermal resistance across the TIM and its adjacent interfaces, tfilm is the thickness of the film, κfilm is the thermal conductivity of the TIM film, and RC is the thermal contact resistance across the bonded interfaces (which is typically assumed to be equal on each side of the interface  and is usually sufficient to describe thermal contact resistance when the TIM is surrounded by similar materials that have been machined in the same way). Based on Eq. (14), the thickness of the film is as important as its thermal conductivity, though there are practical limits to what can be achieved in common electronics packaging systems.
DARPA's recent Nanothermal interfaces program established a goal for next-generation TIMs based on a required thermal resistance across bonded interfaces [348,349]. The program's initial goal was to reduce the total thermal resistance (RT) to values below 1 mm2·K/W, with a future goal of values that fall below 0.1 mm2·K/W. Two recent studies are highlighted to demonstrate the improvements that have been made with nanoparticle-based TIMs, including those based on sintered silver nanoparticles  and BN nanoparticle/copper TIMs . The first study utilizes newly developed steady-state experimental techniques  to demonstrate that an overall thermal resistance of < 0.5 mm2·K/W across copper-sintered silver–copper interfaces. The authors find that the contact thermal resistance is well below 0.1 mm2·K/W with measurement uncertainty of less than 10%. In this case, the target goal of < 1 mm2·K/W is reached through a combination of reductions in thickness of the bonded material (<10 μm) and improvements in TIM thermal conductivity (>300 W/m·K due to the sintering of nanoparticles and a corresponding reduction in phonon boundary scattering). The low contact thermal resistance at the interface is also critical to the reduction in RT, where evaporated nickel-gold plating is used to provide for enhancements in the bond strength between the copper and the TIM itself. In the second study, BN nanoparticles are embedded within a copper matrix material and crosslinked to the Cu via soft organic linkers . The material is fabricated using an electrodeposition technique and the total thermal resistance across a Si/TIM interface ranges between 0.2 and 0.4 mm2·K/W as measured using a modified frequency-domain thermoreflectance technique. The authors widely attribute the reduction in total thermal resistance to enhanced heat flow through the copper matrix due to a reduction in phonon boundary scattering at the BN/Cu interfaces. These TIMs also have relatively high thermal conductivity (–250 W/m·K) and are thin relative to other TIMs (30–50 μm). Ultralow thermal contact resistance (RC) was also achieved by alleviating mismatches in phonon density of states between Si and Cu due to the presence of the soft ligands on the surface of the TIM. In both studies, nanoscale thermal transport is considered at a fundamental level and demonstrates the need for engineering heat flow at nm length scales to achieve further enhancements in heat dissipation through this level of the package.
6.2 Carbon Nanotubes/Polymer Composites (Tian).
Thermal interface materials with high thermal conductivity are in great demand for efficient heat removal from electronic devices. Polymers are widely used as TIMs due to their gap-filling, pliable, and adhesion characteristics, but they typically have low thermal conductivity (–0.1 to 0.4 W/(m·K) [236,352–355]). High-thermal conductivity fillers, such as carbon nanotubes (CNTs), have been used to enhance the effective thermal conductivity of TIMs [353–358].
Due to the significant thermal interface resistance, however, the thermal conductivity of CNT/polymer composites only shows a moderate enhancement of 2–3 times larger than that of amorphous polymers [359–363]. Vertically aligned CNTs (VACNTs) have also been proposed as constituents for thermal conductivity enhancement of polymers. Using CNTs alone, the nonuniform heights across the CNTs create a large thermal contact resistance at adjacent interfaces [344,364]. Aligning CNTs in an amorphous polymer matrix, however, can significantly reduce the thermal contact resistance at VACNT interfaces. Marconnet et al. have demonstrated an enhancement of polymer thermal conductivity up to 4.9 W/(m·K) with the inclusion of VACNTs . Liao et al.  showed that aligned CNT-polyethylene (PE) composites could have a thermal conductivity of –99.5 W/(m·K) with a length of 320 nm, although the cross section of CNT is heavily distorted. Ma and Tian  studied vertically aligned CNTs and PE chains based on equilibrium molecular dynamics. They found that the thermal conductivity of CNT/PE composite along the alignment direction can be as high as 470.1±45.1 W/(m·K), which is about 40% of that of CNT and about 16 times larger than that of PE. This can be well explained by their vibrational density of states. The ultrahigh thermal conductivity of aligned CNT/PE composite may open up exciting opportunities toward enhancing the cross-plane thermal conductivity of polymer-based thermal interface materials for efficient micro-electronics cooling.
7 Nanoscale Energy Transport in Next-Generation Micro-Electronic Systems
Understanding nanoscale thermal transport at both device and integration levels is particularly important for advanced devices whose functionality relies on the thermal modification of material behavior. This section provides an overview of emerging nanoscale devices based on two classes of materials where thermal effects play an integral role in device function: chalcogenide-based phase change materials (PCMs) and thin film metal-oxides.
7.1 Phase-Change Materials for Memory and Data Storage (Ruppalt).
Chalcogenide PCMs derive their useful properties from their ability to reversibly, and nonvolatilely, transition between amorphous and (poly)crystalline solid phases by application of appropriate heat profiles. When the phases exhibit strong electrical or optical contrast, as is the case for many alloys of the Ge-Sb-Te and In-Ag-Sb-Te systems , PCMs can be used to realize a variety of low-power, high performance, switchable or adaptive components. Used for decades as the functional material in optical storage media (e.g., CDs and DVDs) , chalcogenide PCMs have more recently emerged as a critical material component for digital electronic storage [368,369], analog RF devices [370,371], and neuromorphic systems [372,373], as well as for other nascent electronic and optoelectronic applications [374–376].
7.1.1 Phase Change Material-Based Memory.
The most technologically mature electrical use of chalcogenide PCMs is in digital memory devices, with memory products incorporating PCM-based cells already commercially available. For example, 3D X-Point, the memory technology underlying Intel's recently released OptaneTM storage-class memory product, is widely reported to be PCM-based [377,378].
The most common PCM memory architecture integrates a multilayer cross-bar contact array with a single PCM cell at each junction (Fig. 22). Write operations are accomplished by applying an appropriate voltage across the cell, causing Joule heating to occur, which raises the temperature of the PCM sufficiently to switch it into either an electrically conductive polycrystalline phase, or a resistive amorphous phase. Subsequent read operations are possible by applying a low-voltage inter-rogation pulse, which checks resistance of the PCM. Typically, integration of selection devices at each junction is necessary to limit the effects of leakage current during operations on adjacent cells . Electronic memory devices have been demonstrated using a wide variety of PCMs, with Ge-Sb-Te alloys, particularly Ge2Sb2Te5, by far the most well-developed [368,379]. Already, commercialized PCM memory products are reported to outperform nonvolatile NAND-based memory in terms of speed and endurance, and rival volatile DRAM's high device densities , with potential for even further performance improvement.
As the device's switching behavior depends critically on the temperature field within the PCM cell, understanding and controlling thermal transport at the nanoscale is critical for optimizing PCM-based digital memory, particularly as technologists push toward greater device densities to extend the performance of current technologies. Scaling device dimensions to the single-nanometer regime requires enhanced thermal confinement within the PCM cell to reduce heat loss through the electrodes . Indeed, improving efficiency in ultrasmall devices may require integrating atomically thin layers, such as graphene or MoS2, to act as a thermal barrier between the PCM and electrical contacts [381,382]. Furthermore, the thermal gradient within the cell, as well as the impact of non-Joule heating effects, such as thermoelectric heating, can change substantially as device dimensions shrink, new materials are introduced, and interfacial effects increase in significance [383–386]. Characterizing and leveraging the thermal transport in small devices will be especially critical to achieving multilevel memory, which requires the ability to precisely and reproducibly control the temperature profile within the PCM cell to modulate the volume fraction of the cell, which is crystallized or amorphized on each write step [387–389]. These challenges, among many facing PCM memory devices, require an intimate understanding of thermal transport at the nanoscale.
7.1.2 Phase Change Material-Based Radio Frequency Devices.
Chalcogenide PCMs also offer advantages for switchable analog electronic devices. One notable example is the realization of high-performance, nonvolatile RF switches based on GeTe [370,390]. The prototypical PCM-based RF switch includes a PCM segment inserted into a gap in the RF signal line, where the PCM layer can be switched between an insulating amorphous (OFF) state and a conductive polycrystalline (ON) state by applying an electrical pulse to a buried refractory metal heater separated by a dielectric thermal barrier (Fig. 23(a)). A short, high-temperature pulse with a fast fall-time (i.e., quench) raises the PCM temperature above its amorphization temperature and quenches the material into an amorphous phase, while a longer, lower temperature pulse raises the PCM temperature above its crystallization temperature, providing sufficient time and energy for the constituent atoms to organize into a polycrystalline phase (Fig. 23(b)). Using GeTe as the PCM segment, RF switches with insertion losses of the order of 0.1 dB  and cutoff frequencies higher than 10 THz  have been demonstrated.
The utility of PCM-based devices in adaptive RF architectures has already been shown by the demonstration of various reconfigurable RF circuits incorporating GeTe switches, including a reconfigurable bandpass filter  and a multiband receiver . Furthermore, considering the inherently high linearity  and low (i.e., zero) stand-by power of these devices, PCM-based RF switches are viewed as promising components for variety of RF applications requiring low insertion loss, broadband, and power-limited operations. While indirect heating using a buried heater is the most commonly used architecture, PCM-based RF switches have also been demonstrated using direct Joule heating  and optically induced phase transformation .
As the thermal energy necessary to induce phase transition in the PCM segment typically drives the device's power consumption, switching time, and lifetime, current research efforts in PCM-based RF devices are largely directed at lowering the thermal power required for switching. Indeed, thermal engineering by appropriate material selection and device design may be critical to being able to integrate PCM-based RF switches with the reduced power consumption, faster switching speeds, and increased lifetimes required for the most stressing applications. For example, substitution of more thermally conductive AlN for SiN or SiO2 dielectric thermal layers has been shown to reduce device capacitance  and enable integration on arbitrary substrates . Additionally, incorporation of more complex active layers, including quaternary PCMs with optimized electrical properties  or interfacial (or superlattice) PCMs with enhanced crystallization due to interface-mediated nucleation [399,400], may be required to increase switching speeds and lower switching power while retaining RF performance. Modeling of thermal transport in PCM-based RF components, including precise characterization of material properties and interfacial effects , will be critical for evaluating tradeoffs in material selection and device design in these multilayer structures [401,402].
7.1.3 Phase Change Material-Based Neuromorphic Electronics.
The emerging field of neuromorphic computing offers another venue for leveraging the thermally mediated properties of chalcogenide PCMs. Broadly, neuromorphic computing approaches aim to transcend the limitations of conventional, deterministic von Neumann frameworks by implementing devices and architectures that mimic biological function to achieve adaptive, energy-efficient computing . The potential for low-power operation and high device density, as well as the ability to colocate memory and processing, makes PCMs particularly attractive for neuromorphic platforms , and a variety of PCM-based biomimetic devices have already been demonstrated or simulated, including artificial synapses that possess tunable electrical weights [403,404], and artificial integrate-and-fire neurons for generating electrical spiking signals, such as that shown in Fig. 24 [405–407].
Numerous groups have already demonstrated or emulated spike-timing dependent plasticity, a key behavior for many neuromorphic computing paradigms, in PCM-based systems [403,408], and simulations and hardware implementations have shown the utility of PCM-based devices for neuromorphic computing tasks such as visual pattern extraction  and temporal correlation detection . Though the field is in its infancy, the thermal challenges in developing PCM-based neuromorphic electronics mirror those in developing other PCM-based technologies. Device scaling, the introduction of thermally optimized materials, and the use of thermal modeling to direct material selection and device design to control and direct thermal transport will be critical for realizing the dense functional networks necessary to support artificial intelligence and other advanced applications.
7.2 Nanoscale Thermal Transport in Oxides for Neuromorphic Computing (Pahinkar and Graham).
Three terminal MOSFETs have been the fundamental building block of modern electrical circuits. They are demonstrated to be extremely scalable and to follow Moore's law of scaling . However, as more MOSFETs are packed into a smaller space, thermal management of these devices becomes difficult and a new challenge emerges to remove the generated heat and keep the device performance competitive at variable loads. It has been widely reported that electrical design of high density and high-performance electronic devices is possible, yet their fabrication has stalled due to packaging and heat removal constraints at nanometer length scales [412,413].
Therefore, alternative semiconductor technologies, such as memristors, are gaining attention from the wider scientific community. Unlike conventional MOSFETs, the semiconductor materials used for these devices are transition metal oxides, such as TaO2 [414–417], HfO2 [418–424], VO2 [425,426], NbO2 [427–429], and LiNbO2 . The electrical resistances of these oxides depend on the process of redox reactions, in some cases compounded with temperature-assisted hopping . Typically, these devices have two electrode terminals (a sample HfO2 memristor shown in Fig. 25) and the voltage applied at one of the terminals is enough to manipulate the electrical resistance of the oxide material. Such design makes the individual transistor and the complete miniaturized assembly simple and compact by eliminating the third terminal entirely and by making 3D packaging of the devices convenient at the nanoscale.
However, the actual operation of the oxide devices is complex and is a topic of extensive ongoing research. As an example, in case of a fresh HfO2 device, a positive voltage is applied at the top electrode resulting in reduction of the HfO2 molecules in the oxide layer. The oxygen ions that are removed from the oxide layer are attracted toward the positive electrode and are stored in the scavenging layer. The scavenging layer can be synthesized with Ti or Hf, which allows movement of oxygen ions. This ion movement leaves behind a filament of positively charged oxygen vacancies, and vacancies or a metal-like filaments facilitate the flow of electrons through the oxide layer. This is the on-state of the device, also known as set stage . If the top electrode is subsequently biased with negative voltage, a handful of previously removed oxygen ions drift into the filament and neutralize a few monolayers' worth of vacancies, thereby reducing the electrical conductivity of the filament. In this process, oxygen ions are repelled toward the filament due to drift (downward in Fig. 26(a)), whereas the heat generated in the filament pushes the oxygen ions outward in the direction of the positive electrode due to thermophoresis [414,418]. This set of counteracting phenomena results in a controlled movement of ions and therefore a controlled change in the electrical resistance of the filament (also known as reset), thereby making the resistance a function of the applied voltage only. A sample I–V plot is shown in Fig. 26(b), which depicts the reset stage on the left and set stage on the right of V = 0.
For this type of memristive oxide, current flows through a conducting filament with diameter of the order of 5–10 nm. For a 5 nm thick oxide layer conducting 1 mA of current at 0.5 V (point B in Fig. 26(b)), the volumetric heat dissipation through the filament (assuming that it is cylindrical) is greater than 1020 Wm−3. This results in temperatures as high as 1500 K. As resistance of the device is increased due to ion movement, the current drops and further reduces the temperature of the filament, which severely impedes the ion mobility. The reset process is therefore self-limiting and decelerates at high negative voltages. Consequently, the thermal environment of the nanoscale filament and surrounding layers strongly affects the electrical properties of the device. In the memristor community, a device is said to be performing well if the memory window (ratio of the highest resistance to the lowest resistance) is large. This is possible if additional ions are relocated during the reset stage, which depends on continued presence of favorable thermal fields. Therefore, heat must remain trapped inside the device, despite the drop in current as the oxygen ions move. Hence, nanoscale heat transfer in the context of device fabrication must be critically assessed for the development of efficient memristor devices.
There have been several attempts in the past to manipulate the device design by changing the electrode materials, scavenging layer material (Ti), initial oxygen deficiency in the oxide layer, layer thicknesses, substrate materials, and substrate thicknesses. Kim et al.  studied the effect of electrode metals such as Palladium, Rubidium, and Tungsten (thermal conductivities of 72, 117, and 173 W m−1 K−1, respectively) on the current and temperature variation of TaOx (x represents a number less than 2, which means oxygen deficiency) memristors. They reported that the use of low thermal conductivity material top electrode results in high temperature within the filament, which accelerates ion movement. When the Tungsten electrode is replaced by Palladium, the resistance ratio between reset and for 10 pulses changes from 1.37 to 1.67, which is attributed to the heat spreading in the top electrode. A similar effect was observed when the scavenging layer of TaOx was varied in the thickness. A 55% decrease in the thickness of this layer resulted in a 30% increase in the resistance ratio between set and reset for TaOx. While these devices were designed to be only 105 nm thick, the effect of substrate was not considered extensively. Pahinkar et al. reported the effect of substrate materials on the I–V curves for HfOx devices. It was found that the use of a low thermal conductivity substrate like glass can result in a wider memory window for these memristors as a result of more trapped heat. This result was also validated with surface temperature measurement using transient thermal imaging techniques.
With some exceptions, the studies documenting the electrical performance of oxide memristors primarily involve the selection of an oxide material, device fabrication, and metallographic analyses without much emphasis on the effect of packaging and thermal management of these devices. This is because making reliable devices that can compete with the conventional MOSFETs in terms of reliability, power density, and commercial presence is still a distant target. Therefore, most of the studies focus on identifying current transport mechanisms and experimentally validating the same owing to the nascent stage of the relevant research. Hence, there is a tremendous opportunity to understand nanoscale thermal transport within these devices to improve their performance in application. Techniques such as manipulating the development of the oxygen-deficient filament by preferential thermophoresis using low thermal conductivity membranes between electrodes , passive or second-order thermal activation of several filaments , initial oxygen vacancy concentration [433,434], multiple combinations of oxide layers and scavenging layers can be potential avenues to improve device performance as neuromorphic computing research matures.
In this review, the authors demonstrate why nanoscale thermal transport is critical to the development of electronics systems across a wide array of applications. These include wide-bandgap materials and devices, neuromorphic computing, tailorable interface thermal conductance, 2D materials and interfaces, and thermal interface materials in electronics packaging. We show that each application is substantially impacted by nanoscale thermal transport and argue for its incorporation in the design of future devices. The perspectives presented by the authors in this review represent key areas where a firm understanding and ability to manipulate thermal transport is crucial, and will play an important role in the continued development of electronic systems. In the coming years, the ability to tune, control, and manipulate heat at the nanoscale will become increasingly important as electronics continue to scale down in size, and increase power consumption and operational frequency.
RJW and AAW were responsible for writing the Introduction while RJW, AAW, BFD, SD, AG, and PEH edited the work. Each of the remaining coauthors contributed an individual perspective in their area of expertise.
We would also like to acknowledge Dr. Mark Spector from the Office of Naval Research (ONR) for his continued support of many of the research efforts highlighted in this work.
Office of Naval Research (ONR) (Contract No. N0001419WX00312; Funder ID: 10.13039/100000006).
AFOSR Young Investigator Program (Grant No. FA9550-17-1-0141; Funder ID: 10.13039/100000181).
National Science Foundation (Grant No. CBET-1934482; Funder ID: 10.13039/100000001).
ONR Young Investigator Program (Grant No. N00014-18-1-2724; Funder ID: 10.13039/100000006).