Abstract

Direct bonded copper (DBC) substrates used in power modules have limited heat spreading and manufacturing capability due to ceramic properties and manufacturing technology. The ceramic and copper bonding is also subject to high mechanical stress due to coefficient of thermal expansion mismatch between the copper and the ceramic. For wide-bandgap (WBG) devices, it is of interest exploring new substrate technologies that can overcome some of the challenges of direct bonded copper substrates. In this technical paper, the design, analysis, and comparison of insulated metal substrates (IMSs) for high-power wide-bandgap semiconductor-based power modules are discussed. This paper starts with technical description and discussion of state-of-the-art DBC substrates with different ceramic insulators such as aluminum nitride (AlN), Al2O3, and Si3N4. Next, an introduction of IMSs and their material properties, and a design approach for SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET)-based power modules for high-power applications is provided. The influence of dielectric thickness on the power handling capability of the substrate are also discussed. The designed IMS and DBC substrates were characterized in terms of steady-state and transient thermal performance using finite element simulation. Finally, the performance of the IMS and DBC are validated in an experimental setup under different loading and cooling temperature conditions. The simulation and experimental results showed that the IMS can provide high steady-state thermal performance for high-power modules based on SiC MOSFETs. Furthermore, the IMS provided enhanced transient thermal performance, which provided a reduced junction temperature when the module is operated at low fundamental output frequencies in traction drive systems.

1 Introduction

Power semiconductor modules used in power converters are responsible for processing and transferring the electrical power between the source and the load with the desired performance. The efficiency of such systems has become quite high—above 95% for systems rated more than 1 kW output power—because of the recent advancements in silicon-based power semiconductor devices. With the advancements in wide-bandgap (WBG)-based power semiconductor devices such as SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET) and gallium nitride high electron mobility transistor, efficiency figures above 98% have been reported in the literature [1,2]. However, even with very high efficiency figures, a significant amount of power is dissipated in a small area because of increased power demand from the electrical load, increased power density of power modules, and smaller WBG chip size [3]. Therefore, the performance of the materials used for packaging, integration of power modules, and design of thermal management systems have become the focus of the next-generation power electronic systems, especially in applications such as electric vehicles and electric aircraft [4]. Technical guidelines in the USDrive Electrical and Electronics Tech Team Roadmap [5] estimate a 2× increase in power handling capability up to 100 kW for the electric traction drive system, and a 1.4× increase in operating temperature (180–250 °C) for the power semiconductor module used in the power electronic converter. Furthermore, the power density of the power electronics is expected to increase by 7.5× (13.4–100 kW/L) compared with 2020 targets.

The power module for high-power systems is designed to accommodate semiconductor dies, provide electrical connection/isolation to/from other components, extract and transfer generated heat in the dies, and protect from environmental conditions (e.g., dust, humidity). The illustration of a conventional power module cross section is presented in Fig. 1, where various components of the structure are highlighted. The structure is composed of different materials such as aluminum for bond wire, copper for electrical terminals, and aluminum nitride (AlN) for ceramic-based direct bonded copper (DBC) substrate. This multilayer, multimaterial-based structure has limited heat extraction capabilities. Furthermore, certain layers in the structure shown in Fig. 1 are subject to high mechanical stress due to different coefficients of thermal expansion (CTEs) between layers during power and environmental cycling of the module, thus leading to limited lifetime and early failures caused by thermal stress [6]. A DBC substrate in the power module provides the two-layer substrate structure in which the top layer is used for die attachment, interconnect, and electrical terminal placement. The bottom layer is insulated from the top layer with a ceramic layer in between and is attached to the base plate, which is designed as a heat spreader. The ceramic has to provide excellent thermal and electrical performance in terms of thermal conductivity and breakdown voltage to transfer the generated heat in the dies to the heat sink, and to isolate the live terminals on top of the DBC from the rest of the system. Various insulator materials have been studied in literature for direct bonded substrates. Fundamental properties of the three most common ceramic materials used in the industry are presented in Table 1.

Fig. 1
Illustration of a conventional power module cross section[6]
Fig. 1
Illustration of a conventional power module cross section[6]
Close modal
Table 1

Standard layer thickness of insulators and fundamental properties [13]

MaterialStandard thickness (μm)Heat transfer coefficient (W/(cm2K))Breakdown voltage (kV)Thermal conductivity (W/(m·K))
Al2O33816.35.724
AlN63528.312.7170
Si3N4635118.960
HT-070061521.41112.2
MaterialStandard thickness (μm)Heat transfer coefficient (W/(cm2K))Breakdown voltage (kV)Thermal conductivity (W/(m·K))
Al2O33816.35.724
AlN63528.312.7170
Si3N4635118.960
HT-070061521.41112.2

In DBC, aluminum oxide is the commonly used isolator in substrate design for which mechanical strength and a relatively high coefficient of thermal expansion are desired and power density is not a concern. The manufacturing of Al2O3 is relatively cheaper than that of AlN because of the existence of an oxide layer on the ceramic to form the bonding between the metal and ceramic. Although the standard thickness for Al2O3 is presented as 381 μ m in Table 1, 500 μ m and 630 μ m values are also encountered for high-voltage designs. Aluminum nitride is the high-performance dielectric option among all the ceramics presented in Table 1 because of high thermal conductivity and breakdown voltage. AlN is two to three times more expensive than Al2O3 and is a brittle material.

The standard thickness of AlN is stated as 630 μ m, and 1 mm thickness is used in very high-voltage applications. Because of the mechanical strength and brittle structure of AlN, 630 μ m thick insulator is commonly used in applications for which a 2–3 kV isolation is required. However, Si3N4 is mechanically stronger than AlN. Therefore, Si3N4 can be machined thinner than standard thickness 630 μ m, which brings the opportunity to match the thermal performance of AlN-based DBC at low-voltage applications, using Si3N4 without compromising the electric isolation performance.

The alternative to using DBC for power electronic applications is to use insulated metal substrate (IMS), in which polymer-based film is used to insulate the conductive layers in the substrate. IMSs have been studied for power modules [712], and the thermal performance of IMS presented in these works is usually lower than the conventional DBC solutions. The main advantages of IMS are the flexible layer thickness for conductive and dielectric layers, ease of manufacturing, and multilayer availability for optimized electrical layouts. HT-07006 is the dielectric polymer/ceramic blend from Henkel that has excellent dielectric strength and can be processed in very thin layers. These two properties make it an attractive solution for high-power applications despite the lower thermal performance than that of ceramic materials. Furthermore, polymer materials have a wide elastic deformation range, and the thermal expansion performance is not of interest in substrate applications [13].

In this paper, the design, analysis, comparison, and experimental validation of IMSs for high-power WBG semiconductor-based power modules are discussed. In Sec. 2, the structure and the design of the IMS, and a structural comparison with AlN-based DBC, will be provided. Next, a discussion of the steady-state and transient finite element-based thermal simulations conducted in comsolmultiphysics will be provided. The junction temperature analysis of the SiC MOSFETs based on different substrates under different load conditions for a traction drive scenario is presented and discussed. Finally, the experimental validation of the thermal performance of IMS in comparison with DBC under steady-state and transient conditions are presented.

2 Insulated Metal Substrate Design for High-Power Modules

The substrate design evaluated in this study is based on a half-bridge SiC MOSFET power module in which three SiC MOSFET dies are paralleled per switch and placed on an electrically isolated substrate from the coolant. The electrical schematic of the half-bridge module is presented in Fig. 2. Kelvin connection for the SiC MOSFETs was used for the gate and source terminal to optimize the switching performance independent of load current. The SiC MOSFET dies used in this work were rated at 900 V, 30 mΩ (CPM3-0900-0030A) at room temperature and manufactured by Wolfspeed (Research Triangle Park, NC). The maximum allowable junction temperature of the die was 175 °C. A traditional DBC substrate was designed to compare the performance with the IMS, shown in Fig. 1. The DBC substrate was formed by a 640 μm AlN ceramic insulator between 300 μm thick copper planes. The semiconductor dies were soldered on different top copper islands and then connected via wire bonds to form a half-bridge power module.

Fig. 2
Electrical layout of the half-bridge module
Fig. 2
Electrical layout of the half-bridge module
Close modal

In this work, IMS was used to replace DBC. The IMS provides flexibility to the designer in terms of the number of stacked layers and thickness in each layer to optimize thermal and electrical isolation performance. Therefore, the flexibility of the design can overcome some of the challenges of IMS such as low thermal conductivity of the dielectric layer, as stated in Table 1. The cross section and isometric views of the insulated metal structure, which was targeted to replace the DBC in Fig. 1, are presented in Figs. 3 and 4, respectively. The SiC MOSFET dies were soldered on two electrically isolated copper cores, which were designed for lateral heat spreading across the substrate to improve transient thermal performance and steady-state thermal resistance. These two copper cores were isolated from the bottom copper layer using the HT-07006 dielectric film, and from each other with nonconductive epoxy-based filler. The thickness of the copper core was 1.6 mm, the dielectric film thickness was 152 μ m, and the bottom layer copper thickness was 70 μ m. The expanded view of the IMS is presented in Fig. 5 where the structure of each layer can be clearly seen. Once the copper core, dielectric layer 1, and bottom layer are bonded, additional layers can be added to the structure. In this case, the dielectric layer 2 and the top layer were added to the design to accommodate isolated electrical terminals for gate-source connections of the SiC MOSFETs and direct current (DC)-terminal for the half-bridge design.

Fig. 3
Illustration of the proposed insulated metal substrate structure for the half-bridge
Fig. 3
Illustration of the proposed insulated metal substrate structure for the half-bridge
Close modal
Fig. 4
Isometric view of the insulated metal substrate
Fig. 4
Isometric view of the insulated metal substrate
Close modal
Fig. 5
Expanded view of the insulated metal substrate
Fig. 5
Expanded view of the insulated metal substrate
Close modal

2.1 Steady-State and Transient Thermal Analysis.

The analyses of the DBC and IMS were conducted with the comsolmultiphysics finite element simulation tool based on representative electrical and thermal operating conditions of a WBG power module. The base temperature of the substrates was set to 65 °C, which is the typical coolant temperature in automotive systems [14]. The heat transfer coefficient between the coolant and the base of the substrate was defined as 5000 W/(m2·K) to represent the cooling performance of a typical liquid-cooled cold plate, and the interface thermal resistance between the substrate and the cold plate [15]. As highlighted in Ref. [16], the thermal performance of power modules is commonly simulated using a constant heat transfer coefficient to represent cooling performance, and a constant source on power dies to represent the conduction and switching losses occurring during power converter operation. According to the SiC MOSFET data sheet, if the proposed module were operated at 400 V DC Link with a 100 A output root-mean-square current and a 30 kHz switching frequency, the sum of conduction and switching loss would be equal to 45 W per switch. Furthermore, if the die area is taken into account (4.08 mm × 3.1 mm), the heat flux is calculated as 356 W/cm2. Considering that the conventional power modules for Si IGBTs can handle 100–150 W/cm2 and targeting 500 W/cm2, the targeted heat flux in this design is comparable to the emerging cooling solutions found in the literature [17]. Therefore, each of the SiC MOSFET dies shown in Fig. 4 was considered as an individual heat source with 45 W constant heat source on the top surface of the die for steady-state thermal analysis. Once the system reached a steady-state, the heat sources were set to 0 W, and the cooling profile of the system was analyzed in a time-dependent simulation for transient thermal response analysis.

For the meshing of the substrates, free triangular mesh was applied at the surface of the system with a 0.2 mm maximum feature size on the die surface and 0.5 mm maximum feature size on the surface of the substrate. The surface mesh was then distributed to five layers in the die, five layers in the die attach, 20 layers in the copper core, five layers in the dielectric layer, and five layers in the bottom layer to capture heat spreading and temperature distribution across the substrate under testing with high accuracy and resolution. Similar settings were applied to the DBC model for consistency. The authors used free triangular mesh on the surface and distributed it along the substrate layers rather than free tetrahedral meshing because of the significant size difference between the substrate size and thickness. The substrate size was 42.7 mm × 45.1 mm and the thickness was 1.8 mm for the IMS and 1.2 mm for the DBC. If tetrahedral meshing were applied for such a geometry, the number of nodes along the thickness of the substrate would be very small unless the element size in tetrahedral mesh was reduced drastically.

The steady-state thermal analysis results for the DBC and IMS are presented in Fig. 6 with the surface temperature distribution for DBC and IMS in Figs. 6(a) and 6(b), and isothermal temperature distribution inside the substrates in Figs. 7(a) and 7(b), respectively. The six SiC MOSFET dies are labeled M1 to M6, as shown in Fig. 4. The DBC provided symmetrical temperature distribution among top and bottom switches in the half-bridge with 144 °C maximum junction temperature on the surface of the die M2. Furthermore, the temperature distribution presented in Fig. 7(a) shows that heat spreading across the DBC was limited, which resulted in hot spot areas around the heat sources. Such temperature distribution across the DBC is one of the reasons for having base plates in conventional power modules. Because the DBC has limited heat spreading capability, a base plate provides a larger surface area for the heat transfer from the dies to the heat sink. However, with the IMS, the maximum junction temperature across the half-bridge module reached 152 °C on the surface of the die M2. The surface temperature distribution in Fig. 6(b) shows that there was an asymmetry in temperature distribution between the top and bottom switches in the half-bridge.

Fig. 6
Steady-state surface temperature distribution results for (a) DBC and (b) IMS based on finite element analysis
Fig. 6
Steady-state surface temperature distribution results for (a) DBC and (b) IMS based on finite element analysis
Close modal
Fig. 7
Steady-state isothermal contours with the structure for the (a) DBC and (b) IMS based on finite element analysis
Fig. 7
Steady-state isothermal contours with the structure for the (a) DBC and (b) IMS based on finite element analysis
Close modal

The M4M6 dies had a lower temperature than the M1M3 dies under the same loading conditions. The reason for this asymmetry can be explained with the design of the copper core in the IMS. As shown in Fig. 5, the copper core was divided into two pieces and separated with a dielectric separator to provide isolated copper islands for the top and bottom switches in the half-bridge configuration. The thermal conductivity of the dielectric separator was less than 0.6 W/(m K), and therefore, the separator also acted as a thermal insulator between two sections of the copper core. Furthermore, Fig. 5 shows that the right side of the copper core was slightly larger than the left side to accommodate the wire bonding of the M1M3 dies and the output terminal of the half-bridge. The increase in the copper core volume led to improved heat spreading for the M4M6 dies, and the thermal separation with the dielectric separator limited the heat transfer between the isolated islands within the copper core. The difference in the temperature distribution in the copper core can be observed in Fig. 7(b).

The transient thermal impedance of each SiC MOSFET die on the IMS and DBC substrates was obtained by recording the cooling performance of each die in a time-dependent simulation. The time-dependent simulation was run for 100 s, and the initial condition for the transient analysis was defined as the results of the presented steady-state analysis. Since the junction temperature of each die could be recorded, the base temperature was fixed to 65 °C and the initial heat loss across each die was fixed to 45 W, and the transient thermal impedance was calculated at every time-step. The transient thermal impedance values of six dies placed on the IMS and DBC substrates are presented in Fig. 8(a) and in Fig. 8(b), respectively. The comparison of the most stressed dies for the IMS and DBC substrates are presented in Fig. 9.

Fig. 8
Transient thermal impedance of each die on the: (a) DBC and (b) IMS
Fig. 8
Transient thermal impedance of each die on the: (a) DBC and (b) IMS
Close modal
Fig. 9
Comparison of transient thermal impedance of M2 and M5 on the DBC and IMS
Fig. 9
Comparison of transient thermal impedance of M2 and M5 on the DBC and IMS
Close modal

Figure 8(a) shows that the symmetrical thermal performance presented in Fig. 6(a) was achieved by the well-matched steady-state thermal impedance for individual dies on the DBC. The steady-state thermal impedance difference among six dies was less than 0.1°K/W. The transient thermal impedance for the dies on the IMS is presented in Fig. 8(b). The impact of the asymmetrical copper core design discussed in Sec. 2.1 can be clearly seen in the steady-state thermal impedance values. Although the thermal impedance difference between paralleled dies was negligible, there was an approximately 0.2 °K/W difference between the paralleled die groups. Finally, the transient thermal impedance comparison of the most stressed M2 and M5 dies is presented in Fig. 9. The comparison results for M2 show that although the small core area provided for M1M3 in the IMS resulted in a higher steady-state thermal impedance, the transient thermal impedance between 10 ms and 1 s improved up to 40% when compared with the DBC-based solution. The results for the M5 die show that if the copper core area is sufficiently large enough, the steady-state thermal impedance of a SiC MOSFET die on an AlN-based DBC can be matched with an IMS solution with 40% improved transient thermal impedance below 1 s.

2.2 Thermal Analysis in an Inverter Scenario.

The transient thermal impedance curve for each die was used in a power electronics simulation tool to evaluate the mean junction temperature Tj and junction temperature variation ΔTj under typical power electronic inverter operating scenarios. The simulation tool consisted of electrical and thermal domains, which were coupled with current-, voltage-, and temperature-dependent semiconductor loss models obtained from the device manufacturer. In the electrical model, the device current and voltage waveforms were simulated to estimate the switching and conduction losses at a given junction temperature defined by the thermal domain. Using the device loss model, the instantaneous power loss was fed in to the thermal model for junction temperature calculation at the next instant. The schematic of the developed model for the thermal analysis of the substrates in an inverter scenario is presented in Fig. 10. A half-bridge inverter topology was selected with a 30 kHz switching frequency, 600 V DC link voltage, and 0.9 modulation index. The output current was set to 100 Arms per substrate (200 Arms total) with a power factor of 0.85 and fundamental period of 50 Hz. In each substrate block, there were six SiC MOSFET losses, Ploss, coupled to the Foster network-based thermal model of an individual die presented in Fig. 2. The Foster network for each die was developed based on curve fitting to the individual transient thermal impedance curves presented in Figs. 8(a) and 8(b). The Foster network-based thermal model for a SiC MOSFET die is presented in Fig. 11 and the network parameters for the dies on the DBC and IMS are presented in Tables 2 and 3, respectively, in the Appendix.

Fig. 10
Schematic of the model for the thermal analysis of the substrates in an inverter scenario
Fig. 10
Schematic of the model for the thermal analysis of the substrates in an inverter scenario
Close modal
Fig. 11
Thermal model of a SiC MOSFET die in the model based on Foster network
Fig. 11
Thermal model of a SiC MOSFET die in the model based on Foster network
Close modal
Table 2

Foster network thermal parameters for dies on the DBC

ImpedanceZth
i12345
M1Rthi (K/W)1.0370.00010430.28470.38680.0008247
τi (s)0.53480.18010.0066430.085640.7555
M2Rthi (K/W)0.43840.51960.27690.49570.007333
τi (s)0.086410.55620.0064920.52890.02078
M3Rthi (K/W)0.0039540.36631.010.00032210.2601
τi (s)0.12350.075530.53450.65920.00595
M4Rthi (K/W)0.24270.94930.37260.082210.001436
τi (s)0.0053790.52560.068570.52360.541
M5Rthi (K/W)0.30190.00014931.0180.14430.2818
τi (s)0.0072850.59030.53760.1140.08627
M6Rthi (K/W)0.10340.18580.075420.27371.078
τi (s)0.0034980.0099380.08360.077540.5159
ImpedanceZth
i12345
M1Rthi (K/W)1.0370.00010430.28470.38680.0008247
τi (s)0.53480.18010.0066430.085640.7555
M2Rthi (K/W)0.43840.51960.27690.49570.007333
τi (s)0.086410.55620.0064920.52890.02078
M3Rthi (K/W)0.0039540.36631.010.00032210.2601
τi (s)0.12350.075530.53450.65920.00595
M4Rthi (K/W)0.24270.94930.37260.082210.001436
τi (s)0.0053790.52560.068570.52360.541
M5Rthi (K/W)0.30190.00014931.0180.14430.2818
τi (s)0.0072850.59030.53760.1140.08627
M6Rthi (K/W)0.10340.18580.075420.27371.078
τi (s)0.0034980.0099380.08360.077540.5159
Table 3

Foster network thermal parameters for dies on the IMS

ImpedanceZth
i12345
M1Rthi (K/W)0.00075171.3310.0034360.30010.263
τi (s)1.331.5930.40720.13470.00628
M2Rthi (K/W)0.24730.25260.13341.2940.0001455
τi (s)0.0058280.096670.23921.5961.712
M3Rthi (K/W)0.26310.054611.1970.33980.001128
τi (s)0.0063671.6321.610.16881.752
M4Rthi (K/W)0.00090160.91540.41570.080990.2625
τi (s)1.371.6520.18451.6770.006316
M5Rthi (K/W)0.42811.657 × 10−60.26540.023131.021
τi (s)0.15611.9810.0064330.58541.63
M6Rthi (K/W)0.36840.029198.675 × 10−51.0280.2766
τi (s)0.18010.34952.0851.6640.006885
ImpedanceZth
i12345
M1Rthi (K/W)0.00075171.3310.0034360.30010.263
τi (s)1.331.5930.40720.13470.00628
M2Rthi (K/W)0.24730.25260.13341.2940.0001455
τi (s)0.0058280.096670.23921.5961.712
M3Rthi (K/W)0.26310.054611.1970.33980.001128
τi (s)0.0063671.6321.610.16881.752
M4Rthi (K/W)0.00090160.91540.41570.080990.2625
τi (s)1.371.6520.18451.6770.006316
M5Rthi (K/W)0.42811.657 × 10−60.26540.023131.021
τi (s)0.15611.9810.0064330.58541.63
M6Rthi (K/W)0.36840.029198.675 × 10−51.0280.2766
τi (s)0.18010.34952.0851.6640.006885

The junction temperature trajectory of the SiC MOSFET dies on the DBC and IMS based on the defined operating scenario are presented in Fig. 12(a). The junction temperature variation frequency is equal to the load frequency. In variable frequency drives used in traction systems, high-current operation is required to produce high torque at very low motor speeds [18]. Therefore, large junction temperature variations may occur across the SiC MOSFET dies in low-speed, high-torque operating regions. To evaluate this effect, the fundamental frequency of the load was swept from 25 to 400 Hz. The mean junction temperature and junction temperature variation using different substrates with respect to load frequency are presented in Figs. 12(b) and 13, respectively. Although the mean junction temperature did not change significantly with the load frequency, it strongly affected the junction temperature variation. At frequencies lower than 100 Hz, the IMS provided a lower junction temperature variation, which will eventually lead to more reliable operation and longer life time. Literature reports that a high number of cycles can be achieved in a power module if the junction temperature is reduced, even if the mean junction temperature is increased in the same amount [19].

Fig. 12
(a) Junction temperature of the most stressed dies at a 50 Hz load frequency and (b) mean junction temperature of the most stressed dies with different load frequencies
Fig. 12
(a) Junction temperature of the most stressed dies at a 50 Hz load frequency and (b) mean junction temperature of the most stressed dies with different load frequencies
Close modal
Fig. 13
Junction temperature variation across the most stressed dies with different load frequencies
Fig. 13
Junction temperature variation across the most stressed dies with different load frequencies
Close modal

3 Experimental Analysis

3.1 Test Setup.

For experimental validation of the IMS concept, test coupons for each technology were manufactured and characterized under a wide range of operating conditions. The experimental setup highlighting the electrical and thermal measurements for the analysis are presented in Figs. 14 and 15(a), respectively.

Fig. 14
Electrical setup of the experimental characterization
Fig. 14
Electrical setup of the experimental characterization
Close modal
Fig. 15
(a) Experimental setup for the substrate characterization and comparison and (b) fabricated IMS sample
Fig. 15
(a) Experimental setup for the substrate characterization and comparison and (b) fabricated IMS sample
Close modal

The electrical setup shown in Fig. 14 was used for power dissipation and thermal loading of the SiC devices on different substrates. During the experimental analysis, the SiC MOSFETs in the half-bridge configuration were turned off by applying −3 V to their gate. Then, a controllable DC current source was connected to DC− and DC+ terminals on the substrate to dissipate power loss across the devices by using a relatively large on-state voltage drop of body diode of SiC MOSFETs. The power loss across the M13 and M46 devices was measured by probing the DC current through the devices and the voltage across the substrate terminals via a power analyzer to ensure symmetrical power loss between the top and bottom devices in the half-bridge.

The thermal measurements were conducted using a high-performance infrared (IR) camera for junction temperature measurement and three precalibrated thermocouples under different locations of the substrate under evaluation. One thermocouple was placed under the M2 die, another under M5, and the last one between M4 and M6 to capture the temperature variation across the substrate. For thermal imaging of the dies and the substrate, the fabricated samples were painted with flat black paint for maximum emissivity and minimum reflection. By using the power loss data from the power analyzer, the average junction temperature from the IR imaging system, and the substrate temperature from the thermocouples, the performance of the substrates were evaluated under different power loss and coolant temperature conditions.

The IMS sample in Fig. 15(b) was painted flat black and mounted on an evaluation board that provided isolated gate circuitry, protection, and high-power connection, as shown in Fig. 16. The experiments were conducted for the IMS and DBC substrates under the same operating conditions. The total power dissipation across six SiC MOSFETs was swept from 0 to 250 W at three different coolant temperatures—25, 45, and 65 °C—in which the flow rate and the coolant temperature were regulated with a closed-loop chiller.

Fig. 16
Test setup board for characterization of IMS and DBC substrates
Fig. 16
Test setup board for characterization of IMS and DBC substrates
Close modal

3.2 Experimental Results.

The experimental results under different testing conditions were used to finalize the comparison and evaluation of the designed IMS with a conventional AlN-based DBC. Under each operating condition, junction temperature rise Tj of each die was recorded on the IR camera, and substrate temperatures at different locations Tbase were recorded along with the total power loss using a power analyzer. The junction temperature rise for DBC- and IMS-based samples at a 25 °C coolant temperature up to 250 W power loss are presented in Figs. 17(a) and 18(a), respectively. The junction temperature rise with respect to the substrate base temperature is expressed as
ΔTj=TjTbase
(1)
Fig. 17
(a) Junction temperature of individual SiC MOSFETs on the DBC substrate with respect to the substrate base at a 25 °C coolant temperature and (b) mean thermal resistance for paralleled SiC MOSFETs at different coolant temperatures
Fig. 17
(a) Junction temperature of individual SiC MOSFETs on the DBC substrate with respect to the substrate base at a 25 °C coolant temperature and (b) mean thermal resistance for paralleled SiC MOSFETs at different coolant temperatures
Close modal
Fig. 18
(a) Junction temperature of individual SiC MOSFETs on the IMS with respect to the substrate base at a 25 °C coolant temperature and (b) mean thermal resistance for paralleled SiC MOSFETs at different coolant temperatures
Fig. 18
(a) Junction temperature of individual SiC MOSFETs on the IMS with respect to the substrate base at a 25 °C coolant temperature and (b) mean thermal resistance for paralleled SiC MOSFETs at different coolant temperatures
Close modal
Using the data shown in Figs. 17(a) and 18(a), the following equations were used to calculate the individual thermal resistance Rth and mean thermal resistance across paralleled dies Rthmean:
Rth=6·dΔTjdPloss
(2)
Rthmean13=Rth1+Rth2+Rth33
(3)
Rthmean46=Rth4+Rth5+Rth63
(4)

The thermal resistance of individual SiC MOSFETs and mean thermal resistance for parallel SiC MOSFETs on the DBC at different coolant temperatures are presented in Figs. 19(a) and 17(b), respectively. The Rth and Rthmean were consistent for all dies at different coolant temperatures, and Fig. 19(a) shows that the middle dies, M2 and M5, showed slightly higher thermal resistance than the rest of the dies. Two possible reasons could exist for this result: (1) The devices were operated in the third operating region of the MOSFET with the intrinsic body diode, which might have led to an asymmetrical current sharing across the M13 and M46 paralleled dies and (2) AlN is a brittle material but not completely rigid; although the 3D-printed house was designed to apply symmetrical clamping pressure to the substrate, the middle dies could have experienced slightly less clamping pressure [20]. Figure 17(b) shows the Rthmean; the figure shows that the thermal resistance across the substrate was symmetrical, and overall power loss and thermal distribution was uniform. The slight increase in Rth and Rthmean (less than 5%) at a 65 °C coolant temperature can be explained with the measurement sensitivity of the nonconductive (IR camera) and conductive (thermocouples) sensing equipment. The IR camera had a ±1 °C accuracy at the given measurement range and the thermocouples had a ±2 °C accuracy.

Fig. 19
Thermal resistance of individual SiC MOSFET with respect to the substrate base at different coolant temperatures on the (a) DBC and (b) IMS samples
Fig. 19
Thermal resistance of individual SiC MOSFET with respect to the substrate base at different coolant temperatures on the (a) DBC and (b) IMS samples
Close modal

The experimental results for the IMS sample are presented in Figs. 18(a), 18(b), and 19(b) for the junction temperature rise, Rth for each SiC MOSFET, and Rthmean for the paralleled SiC MOSFETs, respectively. The thermal resistance for individual SiC MOSFETs in Fig. 19(b) shows that the measurements for all devices under different coolant temperature conditions were consistent. However, similar to the first phenomena discussed for the DBC-based sample, the thermal loading of the paralleled dies is not symmetrical because of the intrinsic body diode performance of the paralleled dies. The mean thermal resistance presented in Fig. 18(b) confirms the clear impact of the asymmetrical copper core distribution underneath the paralleled dies M13 and M46, as predicted with simulation results in Figs. 8(b) and 9. The paralleled dies M13 experienced higher thermal resistance due to a lower copper core in comparison with M46.

The key thermal resistance results from the experimental evaluation of the DBC and IMS are presented together in Fig. 20(a). With adequate copper core placement underneath the SiC MOSFETs, the IMS can match the thermal performance of the DBC because of enhanced heat spreading along the core. The thermal images of the DBC- and IMS-based samples under identical operating conditions for the DBC and IMS are presented in Figs. 20(b) and 20(c), respectively. The temperature profiles presented for both cases in Figs. 20(b) and 20(c) are absolute temperature values measured via IR camera. The clamping pressure applied to the DBC and IMS samples was different and therefore had inherently different contact resistances to the aluminum coldplate shown in Fig. 15(a). The measurement of the substrate temperature via thermocouples decoupled the impact of the clamping effect to the comparison. Therefore, these images should be used in conjunction with the substrate base temperature to evaluate the structure thermal resistance. Both images are scaled for the 100 °C range and from the color distribution among the substrates, lateral heat spreading is concluded to work effectively for the IMS structure.

Fig. 20
(a) Comparison of averaged thermal resistance of paralleled SiC MOSFETs with the IMS and DBC substrates at a 45 °C coolant temperature; thermal images of the (b) DBC sample and (c) IMS sample with a 200 W power loss and 25 °C coolant temperature
Fig. 20
(a) Comparison of averaged thermal resistance of paralleled SiC MOSFETs with the IMS and DBC substrates at a 45 °C coolant temperature; thermal images of the (b) DBC sample and (c) IMS sample with a 200 W power loss and 25 °C coolant temperature
Close modal

To validate the transient thermal impedance analysis presented in Fig. 9, the transient impedance of the setup presented in Fig. 15(a) was measured with the DBC and IMS samples. The comparisons of simulation and experimental results for the DBC and IMS are presented in Figs. 21(a) and 21(b), respectively. Because the experimental measurements match very well with the finite element analysis results in Fig. 10 between 100 and 1 s, the authors conclude that the IMS has enhanced transient impedance in comparison with the DBC. Beyond 1 s, in the experimental results, the effects of the cold plate (additional heat capacitance) and the thermal interface material on the results were observed and therefore were not considered for this comparison.

Fig. 21
Transient impedance performance of the (a) DBC and (b) IMS samples based on simulation results in Figs. 8(a) and 8(b), and experimental measurements
Fig. 21
Transient impedance performance of the (a) DBC and (b) IMS samples based on simulation results in Figs. 8(a) and 8(b), and experimental measurements
Close modal

4 Conclusion

In this work, the design, analysis, comparison, and experimental validation of an IMS for high-power, WBG-based power modules are presented. The design structure and fundamental properties of the IMS are discussed and compared with a conventional DBC substrate using AlN insulators. Finite element analysis-based simulation and comparison of the IMS and DBC with the AlN insulator for a SiC MOSFET-based half-bridge inverter are presented. The steady-state and transient thermal analysis shows that the IMS provided improved heat spreading underneath the SiC MOSFET dies, which provided up to 40% improved transient thermal performance. The transient thermal model for each SiC MOSFET die was generated based on finite element analysis results and used in an inverter scenario for evaluation of the mean junction temperature and junction temperature variation under different operating conditions. The IMS provided reduced junction temperature variation for SiC MOSFETs under low load frequency conditions. IMS- and DBC-based samples were analyzed and characterized experimentally under different coolant temperature and power loss conditions for validation of performance improvements observed in the simulations. The simulation and experimental results concluded that the IMS can be an alternative substrate solution to the DBC for high-power modules, and the IMS can also reduce junction temperature across the semiconductor die at low load frequencies because of increased thermal capacitance across the substrate.

Acknowledgment

This material is based upon work supported by the U.S. Department of Energy, Vehicle Technologies Office, Electric Drive Technologies Program. Authors would like to acknowledge the U.S. Department of Energy's Susan Rogers for managerial support, Oak Ridge National Laboratory's Randy Wiles and Jon Wilkins for CAD design, and Garry Wexler from Henkel for construction of the IMS.

This manuscript has been authored by UT-Battelle, LLC, under Contract No. DE-AC05-00OR22725 with the U.S. Department of Energy (DOE). The DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan.1

Funding Data

  • U.S. Department of Energy (DOE) (Funder ID: 10.13039/100000015).

Nomenclature

     
  • AlN =

    aluminum nitride

  •  
  • DBC =

    direct bonded copper

  •  
  • IMS =

    insulated metal substrate

  •  
  • IR =

    infrared

  •  
  • MOSFET =

    metal-oxide-semiconductor field-effect transistor

  •  
  • Si =

    silicon

  •  
  • SiC =

    silicon carbide

  •  
  • Si3N4 =

    silicon nitride

  •  
  • WBG =

    wide-bandgap

Footnotes

Appendix: Foster Network Parameters

The Foster network thermal parameters for SiC MOSFET dies on the DBC and IMS are presented in Tables 2 and 3, respectively.

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