Abstract
There are numbers of through ceramic vias (TCVs) in ceramic package substrates for vertical interconnection of signal, and it would be very difficult, even impossible, to create the full wave 3D model of all TCVs during signal integrity (SI) analysis of a chip package. Thus, this paper presents a p-type equivalent circuit model for a signal TCV in steady of the full wave 3D model. To improve model accuracy, the model takes into account the parasitic inductance and resistance induced by the skin effect of TCV at high frequencies, as well as the parallel plate effect between multilayer ground plane. A more accurate calculation method of via-plate capacitance is proposed based on the quasi-static method. According to the Feature Selective Verification (FSV) method, the TCV S parameters calculated by the equivalent model and using the via-plate capacitance calculation method proposed in this study are in good consistency with those from HFSS full wave 3D model in a wideband, and the solution time is reduced by 98.85%.
