Abstract
The hybrid substrate (organic interposer + build-up package substrate + solder joints + underfill) of multiple systems and heterogeneous integration is investigated. The organic interposer of the hybrid substrate is fabricated by a fan-out chip-last on a temporary panel with two different kinds of dielectric materials, namely, the photo-imageable dielectric and the Ajinomoto Build-Up Film. These two hybrid substrates are supporting two different chips. The flatness of metal lines of the redistribution-layers, the quality of the hybrid substrate after chip-to-hybrid substrate bonding, and the reliability of the solder joints between these two hybrid substrates will be discussed.
Issue Section:
Research Papers
References
1.
Xilinx/TSMC, 2013, “
Reach -Volume-Production-on-all-28 nm-CoWoS-based-All-Programmable-3D-IC-Families
,” TSMC, Hsinchu, Taiwan, accessed July 27, 2023, https://pr.tsmc.com/english/news/17922.
Stow
,
D.
,
Xie
,
Y.
,
Siddiqua
,
T.
, and
Loh
,
G.
, 2017
, “
Cost-Effective Design of Scalable High-Performance Systems Using Active and Passive Interposers
,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD
), Irvine, CA, Nov. 13–16, pp. 1
–8
.10.1109/ICCAD.2017.82038493.
Yoon
,
S. W.
,
Tang
,
P.
,
Emigh
,
R.
,
Lin
,
Y.
,
Marimuthu
,
P.
, and
Pendse
,
R.
, 2013
, “
Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions
,” 63rd Electronic Components and Technology Conference
, Las Vegas, NV, May 28–31, pp. 1855
–1860
.10.1109/ECTC.2013.65758304.
Chen
,
N. C.
,
Hsieh
,
T.
,
Jinn
,
J.
,
Chang
,
P.
,
Huang
,
F.
,
Xiao
,
J.
,
Chou
,
A.
, and
Lin
,
B.
, 2016
, “
A Novel System in Package With Fan-Out WLP for High Speed SERDES Application
,” 66th Electronic Components and Technology Conference (ECTC
), Las Vegas, NV, May 31–June 3, pp. 1496
–1501
.10.1109/ECTC.2016.435.
Yip
,
L.
,
Lin
,
R.
,
Lai
,
C.
, and
Peng
,
C.
, 2022
, “
Reliability Challenges of High Density Fan-Out Packaging for High-Performance Computing Applications
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 1454
–1458
.10.1109/ECTC51906.2022.002326.
Lin
,
Y.-T.
,
Lai
,
W.
,
Kao
,
C.
,
Lou
,
J.
,
Yang
,
P.
,
Wang
,
C.
, and
Hseih
,
C.
, 2016
, “
Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate
,” 66th Electronic Components and Technology Conference (ECTC
), Las Vegas, NV, May 31–June 3, pp. 13
–18
.10.1109/ECTC.2016.2677.
Yu
,
D.
, 2018
, “
Advanced System Integration Technology Trends
,” Proceedings of SiP Global Summit, SEMICON Taiwan
, Taipei, Taiwan, Sept. 6–8, pp. 1
–18
.10.1109/EDTM.2017.79475988.
Kurita
,
Y.
,
Kimura
,
T.
,
Shibuya
,
K.
,
Kobayashi
,
H.
,
Kawashiro
,
F.
,
Motohashi
,
N.
, and
Kawano
,
M.
, 2010
, “
Fan-Out Wafer-Level Packaging With Highly Flexible Design Capabilities
,” 3rd Electronics System Integration Technology Conference ESTC
, Berlin, Germany, Sept. 13–16, pp. 1
–6
.10.1109/ESTC.2010.56428889.
Motohashi
,
N.
,
Kimura
,
T.
,
Mineo
,
K.
,
Yamada
,
Y.
,
Nishiyama
,
T.
,
Shibuya
,
K.
,
Kobayashi
,
H.
, et al., 2011
, “
System in Wafer-Level Package Technology With RDL-First Process
,” 61st Electronic Components and Technology Conference (ECTC
), Lake Buena Vista, FL, May 31–June 3, pp. 59
–64
.10.1109/ECTC.2011.589849210.
Huemoeller
,
R.
,
Kimura
,
T.
,
Mineo
,
K.
,
Yamada
,
Y.
,
Nishiyama
,
T.
,
Shibuya
,
K.
,
Kobayashi
,
H.
, et al., 2015
, “
Silicon Wafer Integrated Fan-Out Technology
,” Chip Scale Review
, Mar.-Apr. issue, pp. 34
–37
.https://c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2018/01/04_15-Silicon_Wafer_Integrated_Fan-out_Technology.pdf11.
Lim
,
H.
,
Yang
,
J.
, and
Fuentes
,
R.
, 2018
, “
Practical Design Method to Reduce Crosstalk for Silicon Wafer Integrated Fan-Out Technology (SWIFT) Packages
,” 68th Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 29–June 1, pp. 2205
–2211
.10.1109/ECTC.2018.0033212.
Jayaraman
,
S.
, 2022
, “
Advanced Packaging: HDFO for Next Generation Devices
,” Proceedings of IWLPC
, San Jose, CA, Feb., pp. 1
–28
.13.
Suk
,
K.-L.
,
Lee
,
S.
,
Kim
,
J.
,
Lee
,
S.
,
Kim
,
H.
,
Lee
,
S.
,
Kim
,
P.
, et al., 2018
, “
Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications
,” 68th Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 29–June 1, pp. 64
–69
.10.1109/ECTC.2018.0001814.
You
,
S.-H.
,
Jeon
,
S.
,
Oh
,
D.
,
Kim
,
K.
,
Kim
,
J.
,
Cha
,
S.
, and
Kim
,
G.
, 2018
, “
Advanced Fan-Out Package Si/PI/Thermal Performance Analysis of Novel RDL Packages
,” 68th Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 29–June 1, pp. 1295
–1301
.10.1109/ECTC.2018.0019915.
Lin
,
Y.-H.
,
Yew
,
M.
,
Liu
,
M.
,
Chen
,
S.
,
Lai
,
T.
,
Kavle
,
P.
,
Lin
,
C.
, et al., 2019
, “
Multilayer RDL Interposer for Heterogeneous Device and Module Integration
,” 69th Electronic Components and Technology Conference (ECTC
), Las Vegas, NV, May 28–31, pp. 931
–936
.10.1109/ECTC.2019.0014516.
Lin
,
P.-Y.
,
Yew
,
M.
,
Yeh
,
S.
,
Chen
,
S.
,
Lin
,
C.
,
Chen
,
C.
,
Hsieh
,
C.
, et al., 2021
, “
Reliability Performance of Advanced Organic Interposer (CoWoS-R) Packages
,” 71st Electronic Components and Technology Conference (ECTC
), San Diego, CA, June 1–July 4, pp. 723
–728
.10.1109/ECTC32696.2021.0012517.
Lin
,
M. L.
,
Liu
,
M.
,
Chen
,
H.
,
Chen
,
S.
,
Yew
,
M.
,
Chen
,
C.
, and
Jeng
,
S.
, 2022
, “
Organic Interposer CoWoS-R+ (Plus) Technology
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 1
–6
.10.1109/ECTC51906.2022.0000818.
Chang
,
K. T.
,
Huang
,
C.
,
Kuo
,
H.
,
Jhong
,
M.
,
Hsieh
,
T.
,
Hung
,
M.
, and
Wang
,
C.
, 2019
, “
Ultra High Density IO Fan-Out Design Optimization With Signal Integrity and Power Integrity
,” 69th Electronic Components and Technology Conference (ECTC
), Las Vegas, NV, May 28–31, pp. 41
–46
.10.1109/ECTC.2019.0001419.
Lai
,
W.-H.
,
Yang
,
P.
,
Hu
,
I.
,
Liao
,
T.
,
Chen
,
K.
,
Tarng
,
D.
, and
Hung
,
C.
, 2020
, “
A Comparative Study of 2.5D and Fan-Out Chip on Substrate: Chip First and Chip Last
,” 70th Electronic Components and Technology Conference (ECTC
), Orlando, FL, June 3–30, pp. 354
–360
.10.1109/ECTC32862.2020.0006420.
Fang
,
J.-K.
,
Huang
,
M.
,
Tu
,
H.
,
Lu
,
W.
, and
Yang
,
P.
, 2020
, “
A Production-Worthy Fan-Out Solution—ASE FOCoS Chip Last
,” 70th Electronic Components and Technology Conference (ECTC
), Orlando, FL, June 3–30, pp. 290
–295
.10.1109/ECTC32862.2020.0005521.
Cao
,
L.
, 2022
, “
Advanced FOCOS (Fanout Chip on Substrate) Technology for Chiplets Heterogeneous Integration
,” International Electron Devices Meeting (IEDM
), San Francisco, CA, Dec. 3–7, pp. 1
–6
.10.1109/IEDM45625.2022.1001953422.
Cao
,
L.
,
Lee
,
T.
,
Chen
,
R.
,
Chang
,
Y.
,
Lu
,
H.
,
Chao
,
N.
,
Huang
,
Y.
, et al., 2022
, “
Advanced Fanout Packaging Technology for Hybrid Substrate Integration
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 1362
–1370
.10.1109/ECTC51906.2022.0021923.
Lee
,
T.-C.
,
Yang
,
S.
,
Wu
,
H.
, and
Lin
,
Y.
, 2022
, “
Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 1970
–1974
.10.1109/ECTC51906.2022.0030924.
Yin
,
W.-J.
,
Lai
,
W.
,
Lu
,
Y.
,
Chen
,
K.
,
Huang
,
H.
,
Chen
,
T.
,
Kao
,
C.
, and
Hung
,
C.
, 2022
, “
Mechanical and Thermal Characterization Analysis of Chip-Last Fan-Out Chip on Substrate
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 1711
–1719
.10.1109/ECTC51906.2022.0026925.
Lia
,
J.
,
Tsai
,
F.
,
Li
,
J.
,
Pan
,
G.
,
Chan
,
M.
,
Zheng
,
L.
,
Chen
,
S.
, et al., 2021
, “
Large Size Multilayered Fan-Out RDL Packaging for Heterogeneous Integration
,” 3rd Electronics Packaging Technology Conference (EPTC
), Singapore, Dec. 7–9, pp. 239
–243
.10.1109/EPTC53413.2021.966397426.
Miki
,
S.
,
Taneda
,
H.
,
Kobayashi
,
N.
,
Oi
,
K.
,
Nagai
,
K.
, and
Koyama
,
T.
, 2019
, “
Development of 2.3D High Density Organic Package Using Low Temperature Bonding Process With Sn-Bi Solder
,” 69th Electronic Components and Technology Conference (ECTC
), Las Vegas, NV, May 28–31, pp. 1599
–1604
.10.1109/ECTC.2019.0024627.
Murayama
,
K.
,
Miki
,
S.
,
Sugahara
,
H.
, and
Oi
,
K.
, 2020
, “
Electro-Migration Evaluation Between Organic Interposer and Build-Up Substrate on 2.3D Organic Package
,” 70th Electronic Components and Technology Conference (ECTC
), Orlando, FL, June 3–30, pp. 716
–722
.10.1109/ECTC32862.2020.0011828.
Kim
,
J.
,
Choi
,
J.
,
Kim
,
S.
,
Choi
,
J.
,
Park
,
Y.
,
Kim
,
G.
,
Kim
,
S.
, et al., 2021
, “
Cost Effective 2.3D Packaging Solution by Using Fanout Panel Level RDL
,” 71st Electronic Components and Technology Conference (ECTC
), San Diego, CA, June 1–July 4, pp. 310
–314
.10.1109/ECTC32696.2021.0005929.
Lau
,
J. H.
,
Chen
,
G. C.-F.
,
Huang
,
J. Y.-C.
,
Chou
,
R. T.-S.
,
Yang
,
C. C.-L.
,
Liu
,
H.-N.
, and
Tseng
,
T.-J.
, 2021
, “
Hybrid Substrate by Fan-Out RDL-First Panel-Level Packaging
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
11
(8
), pp. 1301
–1309
.10.1109/TCPMT.2021.309678630.
Chen
,
G. C.-F.
,
Lau
,
J. H.
,
Chou
,
R.
,
Yang
,
C.
,
Huang
,
J.
,
Liu
,
N.
, and
Tseng
,
T.
, 2022
, “
2.3D Hybrid Substrate With Ajinomoto Build-Up Film for Heterogeneous Integration
,” 72nd Electronic Components and Technology Conference (ECTC
), San Diego, CA, May 31–June 3, pp. 30
–37
.10.1109/ECTC51906.2022.0001331.
Lau
,
J. H.
, 2022
, “
Recent Advances and Trends in Advanced Packaging
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
12
(2
), pp. 228
–252
.10.1109/TCPMT.2022.314446132.
Lau
,
J. H.
, 2022
, “
Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV-Less Interposer
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
12
(8
), pp. 1271
–1281
.10.1109/TCPMT.2022.319437433.
Lau
,
J. H.
, 2023
, “
Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV-Interposer
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
13
(1
), pp. 3
–25
.10.1109/TCPMT.2023.323400734.
Lau
,
J. H.
, 2023
, “
Recent Advances and Trends in Cu-Cu Hybrid Bonding
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
13
(3
), pp. 399
–425
.10.1109/TCPMT.2023.326552935.
Chou
,
R.
,
Lau
,
J. H.
,
Chen
,
G.
,
Huang
,
J.
,
Yang
,
C.
,
Liu
,
N.
, and
Tseng
,
T.
, 2022
, “
Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill
,” IMAPS Trans., J. Microelectron. Electron. Packag.
,
19
(1
), pp. 8
–17
.10.4071/imaps.154624836.
Peng
,
C.-Y.
,
Lau
,
J. H.
,
Ko
,
C.
,
Lee
,
P.
,
Lin
,
E.
,
Yang
,
K.
,
Lin
,
P.
, et al., 2021
, “
Development of High-Density Hybrid Substrate for Heterogeneous Integration
,” CPMT Symposium Japan (ICSJ
), Kyoto, Japan, Nov. 10–12, pp. 5
–8
.10.1109/ICSJ52620.2021.964886037.
Peng
,
T. C.-Y.
,
Lau
,
J. H.
,
Ko
,
C.-T.
,
Lee
,
P.
,
Lin
,
E.
,
Yang
,
K.-M.
,
Lin
,
B. P.
, et al., 2022
, “
High-Density Hybrid Substrate for Heterogeneous Integration
,” IEEE Trans. Compon., Packag., Manuf. Technol.
,
12
(3
), pp. 469
–478
.10.1109/TCPMT.2022.315184838.
Lau
,
J. H.
, 2021
, “
State of the Art of Lead-Free Solder Joint Reliability
,” ASME Trans., J. Electron. Packag.
,
143
(2
), p. 020803
.10.1115/1.404803739.
Lau
,
J. H.
, and
Lee
,
N.
, 2020
, Assembly and Reliability of Lead-Free Solder Joints
,
Springer
, New York.Copyright © 2024 by ASME
You do not currently have access to this content.
