A chip with 40 nm technology node and beyond generally incorporates low-k/ultra-low-k (LK/ULK) dielectric materials and copper traces in the back end of line (BEOL) to improve its electrical performance. Owing to the fragile low-k/ultra-low-k materials, the BEOL becomes vulnerable to external loads. When a copper pillar bump (CPB) above the BEOL sustains a shear force due to thermal mismatch between the components, failures occur in the microstructures of BEOL, especially in low-k materials. We fabricated CPBs on the chips and investigated fractures in the BEOL by a shear test approach. The shear speed and shear height are varied to examine their effects. The tested samples were analyzed via focused ion beam (FIB) and scanning electron microscope (SEM) to reveal the microstructures degradation or breaks in the BEOL, and they are classified into three kinds of failure modes. Assisted by a finite element analysis (FEA), the failure mechanism was explained and associated with the failure modes. The studies showed that the shear speed has a little influence on the maximum shear stress, but the increase of shear height leads to more fractures in the low-k materials. It indicated that decreasing the height of CPBs is helpful for reducing destruction risk of the BEOL under the thermomechanical loads. Based on a parametric study for shearing test simulation of a single CPB, the modulus and thickness of polyimide (PI) were found a larger impact on the stresses in the low-k material layer, but the modulus of low-k materials has a smaller effect on the stress. Generally, the shear test of a CPB can help to evaluate the integrity of BEOL in a chip.

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