For more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.
Structural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack Retention
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 31, 2018; final manuscript received December 24, 2018; published online February 25, 2019. Assoc. Editor: Jin Yang.
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Geng, P. (February 25, 2019). "Structural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack Retention." ASME. J. Electron. Packag. March 2019; 141(1): 010801. https://doi.org/10.1115/1.4042800
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