The design of three-dimensional (3D) power delivery network (PDN) is constrained by both power and thermal integrity. Through-silicon via (TSV) as an important part of transmission power and heat in stack, the rational design of TSV layout is particularly important. Using minimal TSV area to achieve the required 3D PDN is significant to reduce manufacturing costs and increase integration. In this paper, we propose electrical and thermal models of 3D PDN, respectively, and we use them to solve the 3D voltage drop and temperature distribution problems. The accuracy and efficiency of our proposed methods are demonstrated by simulation measurement. Combining these two methods, a layer-based optimization solution is developed and allows us to adjust the TSV density for different layers while satisfying the global power and thermal constraints. This optimization is scalable and has the same guiding value for multichip stacks with different functions and constraints. A setup of four-chip stack is used to demonstrate the feasibility of this optimization and a large TSV area saving is achieved by this method.

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