The diamond abrasive process which is applied onto the silicon wafer edge, the so called “edge trimming,” is an important step in three-dimensional microelectronics processing technology, due to the significant thickness reduction of the wafer after thinning. Nevertheless, the wafer edge defects caused by edge trimming have often been overlooked. Although the mechanisms of the formation of the defects in Si due to trimming may be similar to the ones caused by grinding, an in-depth study and risk assessment have not been done yet. In addition, the variety of stress relief processing options can give different morphology and defect removal behavior on the edge trimmed Si sidewall. In a first study, we used transmission electron microscopy and Raman spectroscopy to analyze the defects caused by edge trimming. We show the presence of a continuous layer of amorphous Si and of different phases of Si, caused by edge trimming. A comparison of the damage induced in the Si by two different integration schemes is also discussed. When polishing is used for stress release, the observed sidewall defects stay, since the polishing force is only applied on the top surface of the wafer. On the other hand, the damage is completely removed for the case of wet and dry etching. The surface chemical reactions occurring at the surface during these processes are also acting on the Si sidewall. These findings provide a workable edge trimming and stress relief method for permanently bonded wafers, with many industrial applications.
Edge Trimming Induced Defects on Direct Bonded Wafers
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 11, 2017; final manuscript received February 14, 2018; published online May 11, 2018. Assoc. Editor: Yi-Shao Lai.
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Inoue, F., Jourdain, A., Peng, L., Phommahaxay, A., Kosemura, D., De Wolf, I., Rebibis, K. J., Miller, A., Sleeckx, E., and Beyne, E. (May 11, 2018). "Edge Trimming Induced Defects on Direct Bonded Wafers." ASME. J. Electron. Packag. September 2018; 140(3): 031004. https://doi.org/10.1115/1.4040002
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