The effect of applied current in enhancing bonding was studied in Cu-to-Cu direct bonding using Cu microbumps. A daisy-chain structure of electroplated Cu microbumps (20 μm × 20 μm) was fabricated on Si wafer. Cu-to-Cu bonding was performed in ambient atmosphere at 200–300 °C for 10 min under 260 MPa, during which direct current of 0–10 A (2.5 × 106 A/cm2) was applied. With increasing applied current, the contact resistance decreased and the shear strength in the Cu-to-Cu joints increased. The enhanced bonding imparted by the application of current was ascribed to Joule heating and electromigration effects. Subsequently, the joint temperature was calibrated to isolate the electromigration effects for study. In Cu-to-Cu joints joined at the same adjusted temperature, increasing the current caused unbonded regions to decrease and regions of cohesive failure to increase. The enhanced diffusion across the Cu/Cu interfaces under the applied current was the main mechanism whereby the quality of the Cu-to-Cu joints was improved.

References

References
1.
Lim
,
G.-T.
,
Kim
,
B.-J.
,
Lee
,
K.
,
Kim
,
J.
,
Joo
,
Y.-C.
, and
Park
,
Y.-B.
,
2009
, “
Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps
,”
J. Electron. Mater.
,
38
(
11
), pp.
2228
2233
.
2.
Kim
,
S.-C.
, and
Kim
,
Y.-H.
,
2013
, “
Review paper: Flip Chip Bonding With Anisotropic Conductive Film (ACF) and Nonconductive Adhesive (NCA)
,”
Curr. Appl. Phys.
,
13
(
Suppl. 2
), pp.
S14
S25
.
3.
Kim
,
Y. H.
,
Ma
,
S. W.
, and
Kim
,
Y.-H.
,
2014
, “
Chip to Chip Bonding Using Cu Bumps Capped With Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints
,”
J. Electron. Mater.
,
43
(
9
), pp.
3296
3306
.
4.
Orii
,
Y.
,
Toriyama
,
K.
,
Noma
,
H.
,
Oyama
,
Y.
,
Nishiwaki
,
H.
,
Ishida
,
M.
,
Nishio
,
T.
,
LaBianca
,
N. C.
, and
Feger
,
C.
,
2009
, “
Ultrafine-Pitch C2 Flip Chip Interconnections With Solder-Capped Cu Pillar Bumps
,”
IEEE 59th Electronic Components and Technology Conference
(
ECTC
), San Diego, CA, May 26–29, pp.
948
953
.
5.
Sa
,
Y. K.
,
Yoo
,
S.
,
Shin
,
Y. S.
,
Han
,
M. K.
, and
Lee
,
C. W.
,
2010
, “
Joint Properties of Solder Capped Copper Pillars for 3D Packaging
,”
IEEE 60th Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, June 1–4, pp.
2019
2024
.
6.
Ma
,
S. W.
,
Lee
,
J. H.
,
Lee
,
J. S.
,
Kim
,
K. B.
,
Suh
,
M. S.
,
Kim
,
N. S.
, and
Kim
,
Y.-H.
,
2014
, “
Reliability of Cu to Cu Joints Fabricated Using SnAg Capping Layer for 3D TSV Applications
,”
Adv. Mater. Res.
,
900
, pp.
711
714
.
7.
Alam
,
M.
, and
Gupta
,
M.
,
2014
, “
Development of Extremely Ductile Lead-Free Sn-Al Solders for Futuristic Electronic Packaging Applications
,”
Electron. Mater. Lett.
,
10
(
2
), pp.
515
524
.
8.
Kato
,
T.
,
Suzuki
,
K.
, and
Miura
,
H.
,
2017
, “
Effect of the Crystallinity on the Electromigration Resistance of Electroplated Copper Thin-Film Interconnections
,”
ASME J. Electron. Packag.
,
139
(
2
), p.
020911
.
9.
Lau
,
J. H.
,
2016
, “
Recent Advances and New Trends in Flip Chip Technology
,”
ASME J. Electron. Packag.
,
138
(
3
), p.
030802
.
10.
Agarwal
,
R.
,
Zhang
,
W.
,
Limaye
,
P.
,
Labie
,
R.
,
Dimcic
,
B.
,
Phommahaxay
,
A.
, and
Soussan
,
P.
,
2010
, “
Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking
,”
IEEE 60th Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, June 1–4, pp.
858
863
.
11.
Shimote
,
Y.
,
Iwasaki
,
T.
,
Watanabe
,
M.
,
Baba
,
S.
, and
Kimura
,
M.
,
2014
, “
The Fine Pitch Cu-Pillar Bump Interconnect Technology Utilizing NCP Resin, Achieving the High Quality and Reliability
,”
Trans. Jpn. Inst. Electron. Packag.
,
7
(
1
), pp.
87
93
.
12.
Rong
,
Y.
,
Cai
,
J.
,
Wang
,
S.
, and
Jia
,
S.
,
2009
, “
Low temperature Cu-Sn Bonding by Isothermal Solidification Technology
,”
IEEE International Conference on Electronic Packaging Technology and High Density Packaging
(
ICEPT-HDP
), Beijing, China, Aug. 10–13, pp.
96
98
.
13.
Huang
,
M.
,
Yeow
,
O. G.
,
Poo
,
C. Y.
, and
Jiang
,
T.
,
2008
, “
Intermetallic Formation of Copper Pillar With Sn-Ag-Cu for Flip-Chip-on-Module Packaging
,”
IEEE Trans. Compon. Packag. Technol.
,
31
(
4
), pp.
767
775
.
14.
Tadepalli
,
R.
,
Turner
,
K. T.
, and
Thompson
,
C. V.
,
2008
, “
Effects of Patterning on the Interface Toughness of Wafer-Level Cu–Cu Bonds
,”
Acta Mater.
,
56
(
3
), pp.
438
447
.
15.
Ang
,
X. F.
,
Lin
,
A. T.
,
Wei
,
J.
,
Chen
,
Z.
, and
Wong
,
C. C.
,
2008
, “
Low Temperature Copper-Copper Thermocompression Bonding
,”
Tenth Electronics Packaging Technology Conference
(
EPTC
), Singapore, Dec. 9–12, pp.
399
404
.
16.
Kim
,
T. H.
,
Howlader
,
M. M. R.
,
Itoh
,
T.
, and
Suga
,
T.
,
2003
, “
Room Temperature Cu–Cu Direct Bonding Using Surface Activated Bonding Method
,”
J. Vac. Sci. Technol. A
,
21
(
2
), pp.
449
453
.
17.
Wang
,
P. I.
,
Lee
,
S. H.
,
Parker
,
T. C.
,
Frey
,
M. D.
,
Karabacak
,
T.
,
Lu
,
J. Q.
, and
Lu
,
T. M.
,
2009
, “
Low Temperature Wafer Bonding by Copper Nanorod Array
,”
Electrochem. Solid-State Lett.
,
12
(
4
), pp.
H138
H141
.
18.
Lannon
,
J.
,
Gregory
,
C.
,
Lueck
,
M.
,
Huffman
,
A.
, and
Temple
,
D.
,
2009
, “
High Density Cu-Cu Interconnect Bonding for 3-D Integration
,”
IEEE 59th Electronic Components and Technology Conference
(
ECTC
), San Diego, CA, May 26–29, pp.
355
359
.
19.
Tang
,
Y.-S.
,
Chang
,
Y.-J.
, and
Chen
,
K.-N.
,
2012
, “
Wafer-Level Cu–Cu Bonding Technology
,”
Microelectron. Reliab.
,
52
(
2
), pp.
312
320
.
20.
Kim
,
B.
,
Matthias
,
T.
,
Burgstaller
,
D.
,
Zhu
,
S.
,
Kettner
,
P.
,
Jang
,
E.-J.
,
Kim
,
J.-W.
, and
Park
,
Y.-B.
,
2010
, “
Cu-Cu Thermo-Compression Bonding for TSV Integration
,”
ECS Trans.
,
27
(
1
), pp.
813
818
.
21.
Tan
,
C. S.
, and
Chong
,
G. Y.
,
2013
, “
High Throughput Cu-Cu Bonding by Non-Thermo-Compression Method
,”
IEEE 63rd Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, May 28–31, pp.
1158
1164
.
22.
Ruythooren
,
W.
,
Beltran
,
A.
, and
Labie
,
R.
,
2007
, “
Cu-Cu Bonding Alternative to Solder Based Micro-Bumping
,”
Ninth Electronics Packaging Technology Conference
(
EPTC
), Singapore, Dec. 10–12, pp.
315
318
.
23.
Chen
,
K. N.
,
Xu
,
Z.
, and
Lu
,
J.-Q.
,
2011
, “
Demonstration and Electrical Performance Investigation of Wafer-Level Cu Oxide Hybrid Bonding Schemes
,”
IEEE Electron Device Lett.
,
32
(
8
), pp.
1119
1121
.
24.
Shigetou
,
A.
,
Itoh
,
T.
, and
Suga
,
T.
,
2006
, “
Bumpless Interconnect of Ultrafine Cu Electrodes by Surface Activated Bonding (SAB) Method
,”
Electron. Commun. Jpn.
,
89
(
12
), pp.
34
42
.
25.
Oprins
,
H.
,
Cherman
,
V.
,
Webers
,
T.
,
Salahouelhadj
,
A.
,
Kim
,
S.-W.
,
Peng
,
L.
,
Van der Plas
,
G.
, and
Beyne
,
E.
,
2017
, “
Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding
,”
ASME J. Electron. Packag.
,
139
(
1
), p.
011008
.
26.
Shin
,
C.
,
Ma
,
S. W.
,
Lee
,
J. H.
,
Kim
,
K. B.
,
Suh
,
M.
,
Kim
,
N.
, and
Kim
,
Y.-H.
,
2015
, “
Current-Assisted Direct Cu/Cu Joining
,”
Scr. Mater.
,
104
, pp.
21
24
.
27.
Lee
,
J. S.
,
Byun
,
K. Y.
,
Chung
,
Q. H.
,
Suh
,
M. S.
,
Kim
,
S. C.
, and
Kim
,
Y.-H.
,
2009
, “
Chip to Chip Bonding Using Micro-Cu Bumps With Sn Capping Layers
,”
European Microelectronics and Packaging Conference
(
EMPC
), Rimini, Italy, June 15–18, pp.
1
5
.http://ieeexplore.ieee.org/document/5272982/
28.
Lee
,
S. H.
,
Roh
,
H. R.
,
Chen
,
Z. G.
, and
Kim
,
Y.-H.
,
2005
, “
Contact Resistance and Shear Strength of the Solder Joints Formed Using Cu Bumps Capped With Sn or Ag/Sn Layer
,”
J. Electron. Mater.
,
34
(
11
), pp.
1446
1454
.
29.
Chen
,
S.
,
Ke
,
F.
,
Zhou
,
M.
, and
Bai
,
Y.
,
2007
, “
Atomistic Investigation of the Effects of Temperature and Surface Roughness on Diffusion Bonding Between Cu and Al
,”
Acta Mater.
,
55
(
9
), pp.
3169
3175
.
30.
Chen
,
K.-N.
,
Lee
,
S. H.
,
Andry
,
P. S.
,
Tsang
,
C. K.
,
Topol
,
A. W.
,
Lin
,
Y.-M.
,
Lu
,
J.-Q.
,
Young
,
A. M.
,
Ieong
,
M.
, and
Haensch
,
W.
,
2006
, “
Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits
,”
IEEE International Electron Devices Meeting
(
IEDM
), San Francisco, CA, Dec. 11–13, pp.
1
4
.
31.
Chen
,
K. N.
,
Tan
,
C. S.
,
Fan
,
A.
, and
Reif
,
R.
,
2005
, “
Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration During Current Stressing
,”
Appl. Phys. Lett.
,
86
(
1
), p.
011903
.
32.
Dogruoz
,
M. B.
,
2016
, “
Assessment of Joule Heating and Temperature Distribution on Printed Circuit Boards Via Electrothermal Simulations
,”
ASME J. Electron. Packag.
,
138
(
2
), p.
021004
.
33.
Hill
,
A.
, and
Wallach
,
E. R.
,
1989
, “
Modelling Solid-State Diffusion Bonding
,”
Acta Metall.
,
37
(
9
), pp.
2425
2437
.
34.
Im
,
S.
, and
Banerjee
,
K.
,
2000
, “
Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
,”
IEEE International Electron Devices Meeting
(
IEDM
), San Francisco, CA, Dec. 10–13, pp.
727
730
.
35.
Black
,
J. R.
,
1969
, “
Electromigration: A Brief Survey and Some Recent Results
,”
IEEE Trans. Electron Devices
,
16
(
4
), pp.
338
347
.
36.
Hu
,
C. K.
,
Rosenberg
,
R.
, and
Lee
,
K. Y.
,
1999
, “
Electromigration Path in Cu Thin-Film Lines
,”
Appl. Phys. Lett.
,
74
(
20
), pp.
2945
2947
.
37.
38.
Aizawa
,
T.
,
Okagawa
,
K.
, and
Kashani
,
M.
,
2013
, “
Application of Magnetic Pulse Welding Technique for Flexible Printed Circuit Boards (FPCB) Lap Joints
,”
J. Mater. Process. Technol.
,
213
(
7
), pp.
1095
1102
.
You do not currently have access to this content.