Fine pitch interconnects when used with two-dimensional (2D)/2.5D packaging technology offer enormous potential toward decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased level of stresses within the far back end of line (FBEOL) layers of the chip is the primary concern. Seven different types of 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between −55 °C and 125 °C. Finite element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad interface. Experimental data in conjunction with mechanical modeling were used to determine a safe level of stress at the aluminum to passivation layer interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2D/2.5D package assembly with fine pitch interconnects. Finally, a reliable low stress configuration, which takes into account all the design changes, has been proposed, which is expected to be robust with very low risk of failure within the FBEOL region.

References

References
1.
Ben Yoo
,
S. J.
,
2015
, “
Heterogeneous 2D and 3D Photonic Integration for Future Chip-Scale Microsystems
,”
Conference on Lasers and Electro-Optics
(
CLEO
), May 10–15, pp. 1–2.
2.
Green
,
D. S.
,
Dohrman
,
C. L.
,
Demmin
,
J.
, and
Tsu-Hsi
,
C.
,
2015
, “
Path to 3D Heterogeneous Integration
,”
IEEE International 3D Systems Integration Conference
(
3DIC
), Sendai, Japan, Aug. 31–Sept. 2, pp. FS7.1–FS7.3.
3.
Misra
,
E.
,
Daubenspeck
,
T.
,
Wassick
,
T.
,
Scott
,
G. J.
,
Tunga
,
K.
,
Lafontant
,
G.
,
Questad
,
D.
,
Osborne
,
G.
, and
Sullivan
,
T.
,
2012
, “
Novel Design and Integration Enhancements in the Final Polymeric Passivation for Improved Mechanical Performance and C4 Electromigration in Lead-Free C4 Products
,”
IEEE 62nd Electronic Components and Technology Conference
(
ECTC
), San Diego, CA, May 29–June 1, pp.
571
576
.
4.
Raghavan
,
S.
,
Schmadlak
,
I.
,
Leal
,
G.
, and
Sitaraman
,
S. K.
,
2014
, “
Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation
,”
IEEE Trans. Device Mater. Reliab.
,
14
(
1
), pp.
57
65
.
5.
Misra
,
E.
,
Daubenspeck
,
T.
,
Wassick
,
T.
,
Tunga
,
K.
, and
Questad
,
D.
,
2014
, “
FBEOL No-Aluminum Pad Integration in Pb-Free C4 Products for Environmental, Cost and Reliability Benefits
,”
IEEE 14th Electronic Components and Technology Conference
(
ECTC
), Lake Buena Vista, FL, May 27–30, pp.
1949
1954
.
6.
Misra
,
E.
,
Daubenspeck
,
T.
,
Wassick
,
T.
,
Tunga
,
K.
,
Questad
,
D.
,
Osborne
,
G.
,
Shaw
,
T. M.
, and
McLaughlin
,
K.
,
2013
, “
Role of FBEOL Al Pads and Hard Dielectric for Improved Mechanical Performance in Lead-Free C4 Products
,”
IEEE 63rd Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, May 28–31, pp.
2208
2213
.
7.
Li
,
F.
,
Xiao
,
C.
,
He
,
H.
,
Li
,
J.
, and
Zhu
,
W.
,
2016
, “
Investigation on the Defect Induced Thermal Mechanical Stress for TSV
,”
IEEE 17th International Conference on Electronic Packaging Technology
(
ICEPT
), Wuhan, China, Aug. 16–19, pp. 713–715.
8.
Su
,
F.
,
Pan
,
X.
,
Lan
,
T.
,
Guan
,
Y.
,
Ma
,
S.
, and
Chen
,
J.
,
2015
, “
Monitoring the Stress Evolution of Through Silicon Vias During Thermal Cycling With Infrared Photoelasticity
,”
IEEE 16th International Conference on Electronic Packaging Technology
(
ICEPT
), Changsha, China, Aug. 11–14, pp. 603–607.
9.
Lofrano
,
M.
,
Gonzalez
,
M.
,
Guo
,
W.
, and
Van der Plas
,
G.
,
2015
, “
Chip Package Interaction: A Stress Analysis on 3D IC's Packages
,”
IEEE 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems
(
EuroSimE
), Budapest, Hungary, Apr. 19–22, pp.
1
9
.
10.
Sakuma
,
K.
,
Tunga
,
K.
,
Webb
,
B.
,
Ramachandran
,
K.
,
Interrante
,
M.
,
Liu
,
H.
,
Angyal
,
M.
,
Berger
,
D.
,
Knickerbroker
,
J.
, and
Iyer
,
S.
,
2015
, “
An Enhanced Thermo-Compression Bonding Process to Address Warpage in 3D Integration of Large Die on Organic Substrates
,”
65th IEEE Electronics Components and Technology Conference
(
ECTC
), San Diego, CA, May 26–29, pp.
318
324
.
11.
Yong
,
Lv.
,
Zhao
,
A.
, and
Chen
,
C.
,
2015
, “
The Electromigration Failure Mechanism for TSV Process
,”
IEEE China Semiconductor Technology International Conference
(
CSTIC
), Shanghai, China, Mar. 15–16, pp. 1–4.
12.
Darveaux
,
R.
,
2000
, “
Effect of Simulation Methodology on Solder Joint Crack Growth Correlation
,”
IEEE 50th Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, May 21–24, pp.
1048
1058
.
13.
Hu
,
B.
,
Zhou
,
J.
,
Zhou
,
P.
, and
Yang
,
Y.
,
2006
, “
The Effect of Accelerated Thermal Cycle Parameters and the Geometry Dimensions on Solder Joint Reliability
,”
IEEE Conference on High Density Microsystem Design and Packaging and Component Failure Analysis
(
HDP
), Shanghai, China, June 27–30, pp.
242
246
.
You do not currently have access to this content.