Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.
Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits
University of Texas at Arlington,
500 W First Street, Room 211,
Arlington, TX 76019
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received December 16, 2016; final manuscript received March 27, 2017; published online June 12, 2017. Assoc. Editor: Justin A. Weibel.
- Views Icon Views
- Share Icon Share
- Cite Icon Cite
- Search Site
Choobineh, L., Jones, J., and Jain, A. (June 12, 2017). "Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits." ASME. J. Electron. Packag. June 2017; 139(2): 020908. https://doi.org/10.1115/1.4036404
Download citation file:
- Ris (Zotero)
- Reference Manager