In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.
Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received August 11, 2016; final manuscript received December 12, 2016; published online January 10, 2017. Assoc. Editor: Kaushik Mysore.
- Views Icon Views
- Share Icon Share
- Cite Icon Cite
- Search Site
Oprins, H., Cherman, V., Webers, T., Salahouelhadj, A., Kim, S., Peng, L., Van der Plas, G., and Beyne, E. (January 10, 2017). "Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding." ASME. J. Electron. Packag. March 2017; 139(1): 011008. https://doi.org/10.1115/1.4035597
Download citation file:
- Ris (Zotero)
- Reference Manager