First-level and second-level compliant interconnect structures are being pursued in universities and industries to accommodate the differential displacement induced by the coefficient of thermal expansion mismatch between the die and the substrate or between the substrate and the board. The compliant interconnects mechanically decouple the die from the substrate or the substrate from the board, and thus reduce the thermally induced stresses in the assembly. This paper presents drop-test experimental and simulation data for scaled-up prototype of compliant interconnects. The simulations were based on Input-G method and performed using ANSYS® finite element software for varying drop heights. In parallel to the simulations, scaled-up compliant polymer interconnects sandwiched between a polymer die and a polymer substrate were fabricated using three-dimensional (3D) printing, and this fabrication provides a quick low-cost alternative to cleanroom fabrication. The prototype of the assembly was subjected to drop tests from varying drop heights. The response of the assembly during drop testing was captured using strain gauges and an accelerometer mounted on the prototype. The data from the experiments were compared with the predictions from the simulations. Based on such simulations, significant insight into the behavior of compliant interconnects under impact loading was obtained, which could be used for reliable design of compliant interconnect under impact loading. Both the experimental and simulation data reveal that the compliant interconnects are able to reduce the strains that transfer from substrate to die by one-order.

References

References
1.
JEDEC Standard JESD22-B111
,
2013
, “
Board Level Drop Test Method of Components for Handheld Electronic Products
,”
JEDEC Solid State Technology Association
, Arlington, VA, Report No. JESD22-B111.
2.
Luan
,
J.-e.
, and
Tee
,
T. Y.
,
2004
, “
Novel Board Level Drop Test Simulation Using Implicit Transient Analysis With Input-G Method
,”
6th Electronics Packaging Technology Conference
(
EPTC 2004
), Singapore, Dec. 8-10, pp.
671
677
.
3.
Tee
,
T. Y.
,
Luan
,
J.-e.
,
Pek
,
E.
,
Lim
,
C. T.
, and
Zhong
,
Z.
,
2004
, “
Novel Numerical and Experimental Analysis of Dynamic Responses Under Board Level Drop Test
,”
5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems
(EuroSimE 2004), Brussels, Belgium, May 10-12, pp.
133
140
.
4.
Luan
,
J.-e.
, and
Tee
,
T. Y.
,
2005
, “
Effect of Impact Pulse Parameters on Consistency of Board Level Drop Test and Dynamic Responses
,”
55th Electronic Components and Technology Conference
(
ECTC
), Lake Buena Vista, FL, May 31–June 3, pp.
665
673
.
5.
Pan
,
K.
,
Zhou
,
B.
, and
Yan
,
Y.
,
2006
, “
Simulating Analysis of Dynamic Responses for CSP Under Board Level Drop Test
,”
7th International Conference on Electronic Packaging Technology
(
ICEPT’06
), Shanghai, China, Aug. 26–29.
6.
Chen
,
Z.
,
Wang
,
X.
,
Liu
,
Y.
, and
Liu
,
S.
,
2010
, “
Drop Test Simulation of 3D Stacked-Die Packaging With Input-G Finite Element Method
,”
11th International Conference on Electronic Packaging Technology & High Density Packaging
(
ICEPT-HDP
), Xi’an, China, Aug. 16-19, pp.
742
746
.
7.
Wong
,
E.
,
Lim
,
K.
,
Lee
,
N.
,
Seah
,
S.
,
Hoe
,
C.
, and
Wang
,
J.
,
2002
, “
Drop Impact Test—Mechanics & Physics of Failure
,”
4th Electronics Packaging Technology Conference
(
EPTC
), Singapore, Dec. 10-12, pp.
327
333
.
8.
Irving
,
S.
, and
Liu
,
Y.
,
2004
, “
Free Drop Test Simulation for Portable IC Package by Implicit Transient Dynamics FEM
,”
54th Electronic Components and Technology Conference
(
ECTC
), Las Vegas, NV, June 1-4, pp.
1062
1066
.
9.
Lall
,
P.
,
Shantaram
,
S.
,
Angral
,
A.
, and
Kulkarni
,
M.
,
2009
, “
Explicit Submodeling and Digital Image Correlation Based Life-Prediction of Leadfree Electronics Under Shock-Impact
,”
59th Electronic Components and Technology Conference
(
ECTC 2009
), San Diego, CA, May 26–29, pp.
542
555
.
10.
Sun
,
Y.
, and
Pang
,
J. H.
,
2008
, “
Digital Image Correlation for Solder Joint Fatigue Reliability in Microelectronics Packages
,”
Microelectron. Reliab.
,
48
(
2
), pp.
310
318
.
11.
Chen
,
W.
,
Bhat
,
A.
, and
Sitaraman
,
S. K.
,
2013
, “
Use of Compliant Interconnects for Drop Impact Isolation
,”
2013 IEEE 63rd Electronic Components and Technology Conference
(
ECTC
), Las Vega, NV, May 28–31, pp.
835
839
.
12.
Tribe
,
A.
,
Garraway
,
K.
,
Daborn
,
P. M.
, and
Miles
,
K.
,
2007
, “
The Use of Rapid Prototypes for Model Validation
,”
IMAC XXV
,
Orlando, FL
, Feb. 19-22.
13.
Mahn
,
J.
, and
Bayly
,
P.
,
1999
, “
Impact Testing of Stereolithographic Models to Predict Natural Frequencies
,”
J. Sound Vib.
,
224
(
3
), pp.
411
430
.
14.
Lee
,
R. E.
,
Okereke
,
R.
, and
Sitaraman
,
S. K.
,
2011
, “
Multi-Path Fan-Shaped Compliant Off-Chip Interconnects
,”
2011 IEEE 61st Electronic Components and Technology Conference
(
ECTC
), Lake Buena Vista, FL, May 31–June 3, pp.
2141
2145
.
15.
Seah
,
S.
,
Lim
,
C.
,
Wong
,
E.
,
Tan
,
V.
, and
Shim
,
V.
,
2002
, “
Mechanical Response of PCBs in Portable Electronic Products During Drop Impact
,”
4th Electronics Packaging Technology Conference
(
EPTC
), Singapore, Dec. 10-12, pp.
120
125
.
16.
Gibson
,
I.
,
Goenka
,
G.
,
Narasimhan
,
R.
, and
Bhat
,
N.
,
2010
, “
Design Rules for Additive Manufacture
,” International Solid Freeform Fabrication Symposium (
SFF
), Austin, TX, Aug. 9-11, pp.
705
716
.
17.
Chen
,
W.
,
Okereke
,
R.
, and
Sitaraman
,
S. K.
,
2013
, “
Compliance Analysis of Multi-Path Fan-Shaped Interconnects
,”
Microelectron. Reliab.
,
53
(
7
), pp.
964
974
.
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