Solder voids are detrimental to the thermal, mechanical, and reliability performance of integrated circuit (IC) packages and must be controlled within certain specifications. A sequential method of optimizing solder-reflow process to reduce die-attach solder voids in power quad flat no-lead (QFN) packages is presented. The sequential optimization consists, in turn, of theoretical prediction, heat transfer comparison, and experimental validation. First, the theoretical prediction uses calculations to find the optimal pause location and time for a lead frame strip (with dies bonded to it by solder paste) to receive uniform heat transfer during the solder-reflow stage. Next, reflow profiles at different locations on the lead frame strip are measured. Heat transfer during the reflow stage at these locations is calculated from the measured reflow profiles and is compared to each other to confirm the theoretical prediction. Finally, only a minimal number of actual trials are conducted to verify the predicted and confirmed optimal process. Since the theoretical prediction and heat transfer comparison screens out most of the unnecessary trials which must be conducted in common design of experiment (DoE) and trial-and-error methods, the sequential optimization method saves significant time and cost.

References

References
1.
Fleischer
,
A. S.
,
Chang
,
L.-H.
, and
Johnson
,
B. C.
,
2006
, “
The Effect of Die Attach Voiding on the Thermal Resistance of Chip Level Packages
,”
Microelectron. Reliab.
,
46
(
5–6
), pp.
794
804
.10.1016/j.microrel.2005.01.019
2.
Ciampolini
,
L.
,
Ciappa
,
M.
,
Malberti
,
P.
,
Regli
,
P.
, and
Fichtner
,
W.
,
1999
, “
Modeling Thermal Effects of Large Contiguous Voids in Solder Joints
,”
Microelectron. J.
,
30
(
11
), pp.
1115
1123
.10.1016/S0026-2692(99)00073-7
3.
Otiaba
,
K. C.
,
Bhatti
,
R. S.
,
Ekere
,
N. N.
,
Mallik
,
S.
,
Alam
,
M. O.
,
Amalu
,
E. H.
, and
Ekpu
,
M.
,
2012
, “
Numerical Study on Thermal Impacts of Different Void Patterns on Performance of Chip-Scale Packaged Power Device
,”
Microelectron. Reliab.
,
52
(
7
), pp.
1409
1419
.10.1016/j.microrel.2012.01.015
4.
Biswal
,
L.
,
Krishna
,
A.
, and
Sprunger
,
D.
,
2005
, “
Effects of Solder Voids on Thermal Performance of a High Power Electronic Module
,”
7th IEEE Electronics Packaging Technology Conference
(
EPTC 2005
), Singapore, Dec. 7–9, pp.
526
531
.10.1109/EPTC.2005.1614460
5.
Yan
,
Y.
,
Guan
,
Y. L.
,
Chen
,
X.
, and
Lu
,
G. Q.
,
2013
, “
Effects of Voids in Sintered Silver Joint on Thermal and Optoelectronic Performances of High Power Laser Diode
,”
ASME J. Electron. Packag.
,
135
(
4
), p.
041003
.10.1115/1.4025247
6.
Tummala
,
R. R.
,
Rymaszewski
,
E. J.
, and
Klopfenstein
,
A. G.
,
1997
,
Microelectronics Packaging Handbook, Technology Drivers, Part I
,
2nd ed.
,
Chapman and Hall
, New York, pp.
457
508
.
7.
Chang
,
J.
,
Wang
,
L.
,
Dirk
,
J.
, and
Xie
,
X.
,
2006
, “
Finite Element Modeling Predicts the Effects of Voids on Thermal Shock Reliability and Thermal Resistance of Power Device
,”
Weld. J.
,
85
(
3
), pp.
63
70
.
8.
Chiriac
,
V. A.
, and
Yu
,
Y.
,
2010
, “
Impacts of Solder Voids on PQFN Packages' Thermal and Mechanical Performances
,”
12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
(
ITherm
), Las Vegas, NV, June 2–5. 10.1109/ITHERM.2010.5501269
9.
Lee
,
K. K.
,
Yeung
,
N. H.
, and
Chan
,
Y. C.
,
2005
, “
Modeling the Effect of Voids in Anisotropic Conductive Adhesive Joints
,”
Soldering Surf. Mount Technol.
,
17
(
1
), pp.
4
12
.10.1108/09540910510579195
10.
Otiaba
,
K. C.
,
Okereke
,
M. I.
, and
Bhatti
,
R. S.
,
2014
, “
Numerical Assessment of the Effect of Void Morphology on Thermo-Mechanical Performance of Solder Thermal Interface Material
,”
Appl. Therm. Eng.
,
64
(
1–2
), pp.
51
63
.10.1016/j.applthermaleng.2013.12.006
11.
Yu
,
Q.
,
Shibutani
,
T.
,
Kim
,
D.-S.
,
Kobayashi
,
Y.
,
Yang
,
J.
, and
Shiratori
,
M.
,
2008
, “
Effect of Process-Induced Voids on Isothermal Fatigue Resistance of CSP Lead-Free Solder Joints
,”
Microelectron. Reliab.
,
48
(
3
), pp.
431
437
.10.1016/j.microrel.2007.08.008
12.
Ladani
,
L. J.
, and
Dasgupta
,
A.
,
2008
, “
Damage Initiation and Propagation in Voided Joints: Modeling and Experiment
,”
ASME J. Electron. Packag.
,
130
(
1
), p.
011008
.10.1115/1.2837562
13.
Lee
,
N.-C.
,
2001
,
Reflow Soldering Processes and Troubleshooting, SMT, BGA, CSP and Flip Chip Technologies
,
Newnes
, Burlington, MA.
14.
Lee
,
S.
,
Yim
,
M. J.
, and
Baldwin
,
D.
,
2009
, “
Void Formation Mechanism of Flip Chip in Package Using No-Flow Underfill
,”
ASME J. Electron. Packag.
,
131
(
3
), p.
031014
.10.1115/1.3153369
15.
Sadasiva
,
S.
,
Subbarayan
,
G.
,
Jiang
,
L.
, and
Pantuso
,
D.
,
2012
, “
Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects
,”
ASME J. Electron. Packag.
,
134
(
2
), p.
020907
.10.1115/1.4006707
16.
Lee
,
S.
, and
Baldwin
,
D. F.
,
2014
, “
Heterogeneous Void Nucleation Study in Flip Chip Assembly Process Using No-Flow Underfill
,”
ASME J. Electron. Packag.
,
136
(
1
), p.
011005
.10.1115/1.4026164
17.
Lee
,
N.-C.
,
1999
, “
Optimizing the Reflow Profile Via Defect Mechanism Analysis
,”
Soldering Surf. Mount Technol.
,
11
(
1
), pp.
13
20
.10.1108/09540919910254642
18.
Kreuzkamp
,
R.
, and
Reiber
,
T.
,
1998
, “
Improving the Solder Joint Reliability of BGAs
,”
Electron. Packag. Prod.
,
38
(
12
), pp.
45
66
.
19.
Gadepalli
,
H.
,
Dhanasekaran
,
R.
,
Ramkumar
,
S. M.
,
Jensen
,
T.
, and
Briggs
,
E.
,
2009
, “
Influence of Reflow Profile and Pb-Free Solder Paste in Minimizing Voids for Quad Flat Pack No-Lead (QFN) Assembly
,”
IEEE 59th Electronic Components and Technology Conference
(
ECTC 2009
), San Diego, CA, May 26–29, pp.
2016
2024
.10.1109/ECTC.2009.5074299
20.
Ladani
,
L. J.
,
Dasgupta
,
A.
,
Cardoso
,
I.
, and
Monlevade
,
E.
,
2008
, “
Effect of Selected Process Parameters on Durability and Defects in Surface-Mount Assemblies for Portable Electronics
,”
IEEE Trans. Electron. Packag. Manuf.
,
31
(
1
), pp.
51
60
.10.1109/TEPM.2007.914222
21.
Yu
,
Y.
,
Yao
,
S. A.
,
Wang
,
S.
,
Chen
,
W.
, and
Jiang
,
Y. W.
,
2008
, “
Effects of Dispensed Solder Paste Amount on Solder Void Performance in a PQFN Package
,”
11th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
(
ITHERM 2008
), Orlando, FL, May 28–31, pp.
896
900
. 10.1109/ITHERM.2008.4544361
22.
Yu
,
Y.
,
Yao
,
S. A.
,
Lv
,
G. J.
,
Xiao
,
W.
,
Wang
,
S.
,
Jiang
,
Y. W.
, and
Chen
,
W.
,
2008
, “
Effects of Reflow Atmosphere on Solder Void and Wire Bonding Performances in a PQFN Package
,”
11th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
(
ITHERM 2008
), Orlando, FL, May 28–31, pp.
901
905
.10.1109/ITHERM.2008.4544362
23.
Homer
,
S. J.
, and
Lasky
,
R. C.
,
2013
, “
Minimizing Voiding in QFN Packages Using Solder Preforms
,”
Surf. Mount Technol. Mag.
,
28
(
5
), pp.
30
36
.
24.
Yu
,
H.
, and
Kivilathti
,
J.
,
2002
, “
CFD Modelling of the Flow Field Inside a Reflow Oven
,”
Soldering Surf. Mount Technol.
,
14
(
1
), pp.
38
44
.10.1108/09540910210416459
25.
Whalley
,
D. C.
,
2004
, “
A Simplified Reflow Soldering Process Model
,”
J. Mater. Process. Technol.
,
150
(
1–2
), pp.
134
144
.10.1016/j.jmatprotec.2004.01.029
26.
Lau
,
C.-S.
,
Abdullah
,
M. Z.
, and
Khor
,
C. Y.
,
2013
, “
Optimization of the Reflow Soldering Process With Multiple Quality Characteristics in Ball Grid Array Packaging by Using the Grey-Based Taguchi Method
,”
Microelectron. Int.
,
30
(
3
), pp.
151
168
.10.1108/MI-09-2012-0067
27.
Rooks
,
B.
,
2000
, “
Robust Reflow Profile Design
,” Electronic Controls Design (ECD) Inc., Milwaukie, OR, http://www.ecd.com/emfg/instruments/papers/rookspaper.htm
28.
Minitab Inc., 2009, “MINITAB Release 15,” Minitab Inc., State College, PA.
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