Solder voids are detrimental to the thermal, mechanical, and reliability performance of integrated circuit (IC) packages and must be controlled within certain specifications. A sequential method of optimizing solder-reflow process to reduce die-attach solder voids in power quad flat no-lead (QFN) packages is presented. The sequential optimization consists, in turn, of theoretical prediction, heat transfer comparison, and experimental validation. First, the theoretical prediction uses calculations to find the optimal pause location and time for a lead frame strip (with dies bonded to it by solder paste) to receive uniform heat transfer during the solder-reflow stage. Next, reflow profiles at different locations on the lead frame strip are measured. Heat transfer during the reflow stage at these locations is calculated from the measured reflow profiles and is compared to each other to confirm the theoretical prediction. Finally, only a minimal number of actual trials are conducted to verify the predicted and confirmed optimal process. Since the theoretical prediction and heat transfer comparison screens out most of the unnecessary trials which must be conducted in common design of experiment (DoE) and trial-and-error methods, the sequential optimization method saves significant time and cost.
Sequential Reflow-Process Optimization to Reduce Die-Attach Solder Voids
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2013; final manuscript received January 7, 2015; published online January 30, 2015. Assoc. Editor: Paul Conway.
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Yu, Y., Chiriac, V., Jiang, Y., and Wang, Z. (June 1, 2015). "Sequential Reflow-Process Optimization to Reduce Die-Attach Solder Voids." ASME. J. Electron. Packag. June 2015; 137(2): 021013. https://doi.org/10.1115/1.4029569
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