Three-dimensional (3D) chip stacking architecture is expected to reduce form factor, improve performance, and decrease power consumption in future microelectronics. High power density and nonuniform power distribution in stacked dies are expected to bring significant thermal challenges for 3D packages due to localized hot spots. Embedded thermoelectric coolers (TECs) have potential to provide reliable and localized cooling at these hot spots. In this work, peak package temperature or active cooling per power consumption of TECs are optimized, considering applied current and thickness of TECs as parameters, for a 3D electronic package with two stacked dies. Each die has two hot spots and one TEC is paired with each hot spot. Three different optimization methods are considered in order to ensure a robust solution. The optimization suggests that both the peak temperature in package and energy efficiency of the cooling system can be significantly improved through the optimization of TECs. TECs are also compared against a configuration where they are replaced by copper blocks or thermal vias. A total of 4.7 °C of additional localized cooling is observed using TECs which is beyond what is achievable with copper vias in place of the TECs. The study also suggests that it is better to use TECs to cool only the hottest portions of the package to avoid introducing additional thermal resistance and Joule heating in the package.
Optimization of Thermoelectric Coolers for Hotspot Cooling in Three-Dimensional Stacked Chips
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 6, 2014; final manuscript received August 7, 2014; published online October 6, 2014. Assoc. Editor: Madhusudan Iyengar.
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Redmond, M., and Kumar, S. (October 6, 2014). "Optimization of Thermoelectric Coolers for Hotspot Cooling in Three-Dimensional Stacked Chips." ASME. J. Electron. Packag. March 2015; 137(1): 011006. https://doi.org/10.1115/1.4028254
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