In the latest microelectronics industry, the emerging three-dimensional (3D) chip stacking technique using through silicon via (TSV) enables higher integration density that allows greater numbers of interconnections in order to fulfill the urgent requirements of dimensional downscaling and electrical speed enhancement. A high-density pitch of microbumps associated with the wafer-level underfill (WLUF) under a thermal compressions process are utilized to prevent the thermomechanical failures of the microbumps due to variations of thermal expansions of different materials in the 3D package. The use of dummy microbumps has been proposed to find the acceptable thin-layer uniformity and the reliable mechanical performances of the entire packaging structure. The warpage and strain behavior of packaging structure has been simulated by finite element analysis (FEA) and compared with experimental results. The responses were parametrically modeled using Kriging model with respect to compressive force, the thickness of the top chip, and the location of the dummy microbumps. The deterministic design guidance for warpage and strain has been obtained from the Kriging model. Furthermore, the reliability of the design under uncertainty has been investigated. A reliability-based design guidance (RBDG) has been proposed to provide a safety boundary in terms of the allowable reliability index. The proposed method can be utilized as the reliability standard for high-throughput production of 3D integrated circuits (ICs) packaging.

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