Three-dimensional (3D) stacking of integrated-circuit (IC) dies increases system density and package functionality by vertically integrating two or more dies with area-array through-silicon-vias (TSVs). This reduces the length of global interconnects and the signal delay time and allows improvements in energy efficiency. However, the accumulation of heat fluxes and thermal interface resistances is a major limitation of vertically integrated packages. Scalable cooling solutions, such as two-phase interlayer cooling, will be required to extend 3D stacks beyond the most modest numbers of dies. This paper introduces a realistic 3D chip stack along with a simulation method for the heat spreading and flow distribution among the channels of the evaporators. The model includes the significant sensitivity of each channel's friction factor to vapor quality, and hence mass flow to heat flux, which characterizes parallel two-phase flows. Simulation cases explore various placements of hot spots within the stack and effects which are unique to two-phase interlayer cooling. The results show that the effect of hot spots on individual dies can be mitigated by strong interlayer heat conduction if the relative position of the hot spots is selected carefully to result in a heat load and flow which are well balanced laterally.

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