Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.
Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 7, 2013; final manuscript received January 27, 2014; published online February 18, 2014. Assoc. Editor: Shidong Li.
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Liu, D., and Park, S. (February 18, 2014). "Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art." ASME. J. Electron. Packag. March 2014; 136(1): 014001. https://doi.org/10.1115/1.4026615
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