The electronics industry is heading toward the three-dimensional (3D) microprocessor to cope with higher computing workloads. The 3D stacking of the processor and the memory components reduces the communication delay in multicore system-on-a-chip (SoCs), owing to reduced system size and shorter interconnects. The shorter interconnects in a multicore system lowers the memory access latencies and contributes to improvements in memory access bandwidth. The shorter interconnects in stacked architectures also enables small drivers for interconnections which further reduce interconnection-level-energy dissipations. On the down side, the 3D-stacked architectures have high thermal resistance, which in conjunction with poor thermal management techniques, poses a thermal threat to the reliability of the device. This paper establishes the significance of the microprocessor floor planning and single-phase microchannel cooling for solving the thermal issues arising in the 3D-stacked-quad-core processor. The 3D-stacked-quad-core processor considered in this study comprises of symmetric nonuniformly powered quad-core processor, liquid-cooled microchannel heat sink, dynamic random access memory (DRAM), thermal interface material (TIM), and heat spreader. The electrical through-silicon-vias (TSVs) between the processor and DRAM serve as interconnects, while the thermal TSVs reduce the internal thermal resistance. The effective cooling of the 3D-stacked-quad-core processor depends on the TSVs, quad-core layout and the optimized design of the microchannel heat sink for the desired coolant. The microchannel cooling of the 3D-stacked processor is done both by planar flow and impingement flow. The thermal efficiency of the cooling techniques is evaluated on the basis of hot spot temperature, hot spot spread, and number of hot spots.
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December 2013
Research-Article
Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias
Anjali Chauhan,
Anjali Chauhan
1
e-mail: achauha1@binghamton.edu
1Corresponding author.
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Bahgat Sammakia,
Furat F. Afram,
Gamal Refai-Ahmed,
Gamal Refai-Ahmed
Professor
e-mail: gra1963@yahoo.com
SUNY,
e-mail: gra1963@yahoo.com
Small Scale Systems Integration and Packaging Center
,SUNY,
Binghamton, NY 13902
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Dereje Agonafer
Dereje Agonafer
Department of Mechanical and
Aerospace Engineering,
e-mail: agonafer@uta.edu
Aerospace Engineering,
University of Texas at Arlington
,Arlington, TX 76019
e-mail: agonafer@uta.edu
Search for other works by this author on:
Anjali Chauhan
e-mail: achauha1@binghamton.edu
Bahgat Sammakia
e-mail: bahgat@binghamton.edu
Furat F. Afram
e-mail: fafram1@binghamton.edu
Kanad Ghose
e-mail: ghose@cs.binghamton.edu
Gamal Refai-Ahmed
Professor
e-mail: gra1963@yahoo.com
SUNY,
e-mail: gra1963@yahoo.com
Small Scale Systems Integration and Packaging Center
,SUNY,
Binghamton, NY 13902
Dereje Agonafer
Department of Mechanical and
Aerospace Engineering,
e-mail: agonafer@uta.edu
Aerospace Engineering,
University of Texas at Arlington
,Arlington, TX 76019
e-mail: agonafer@uta.edu
1Corresponding author.
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 30, 2012; final manuscript received August 8, 2013; published online November 5, 2013. Assoc. Editor: Mehmet Arik.
J. Electron. Packag. Dec 2013, 135(4): 041006 (14 pages)
Published Online: November 5, 2013
Article history
Received:
November 30, 2012
Revision Received:
August 8, 2013
Citation
Chauhan, A., Sammakia, B., Afram, F. F., Ghose, K., Refai-Ahmed, G., and Agonafer, D. (November 5, 2013). "Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias." ASME. J. Electron. Packag. December 2013; 135(4): 041006. https://doi.org/10.1115/1.4025531
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