This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.
Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 19, 2012; final manuscript received March 23, 2013; published online June 4, 2013. Assoc. Editor: Yi-Shao Lai.
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Okereke, R., Kacker, K., and Sitaraman, S. K. (June 4, 2013). "Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects." ASME. J. Electron. Packag. September 2013; 135(3): 031004. https://doi.org/10.1115/1.4024112
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