A system of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore processor chips. The analysis is performed on a physical model which incorporates certain salient features of multicore processor. The model has active and background cells laid out in a checkered pattern, and the pattern repeats itself in fine grain active cells. The die has a buried dioxide and a wiring layer stacked on the die body, and heat sources are placed at the wiring layer/buried oxide interface. With this model we explore the effects of various parameters on the target spot temperature. The parameters are the die dimensions, the materials' thermal conductivities, the effective heat transfer coefficients on the die surfaces, the power map, and the spatial resolution with which we view the power and temperature distributions on the die. Closed-form analytical solutions are derived and used to examine the roles of these parameters in creating hot spots. The present paper reports the details of mathematical formulations and steps of temperature calculation. The results for a particular example case are included to illustrate what can be learned from the calculations.
Study on Heat Conduction in a Simulated Multicore Processor Chip—Part I: Analytical Modeling
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received February 26, 2012; final manuscript received November 7, 2012; published online March 28, 2013. Assoc. Editor: Stephen McKeown.
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Nakayama, W. (March 28, 2013). "Study on Heat Conduction in a Simulated Multicore Processor Chip—Part I: Analytical Modeling." ASME. J. Electron. Packag. June 2013; 135(2): 021002. https://doi.org/10.1115/1.4023291
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