Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.
A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems
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Venkatadri, V., Sammakia, B., Srihari, K., and Santos, D. (December 9, 2011). "A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems." ASME. J. Electron. Packag. December 2011; 133(4): 041011. https://doi.org/10.1115/1.4005298
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