Latest electronic component package types are pushing the need to more efficiently remove the dissipated heat using optimized thermal paths going through the printed circuit board (PCB) to reach PCB inner thermal planes. So, to optimize board cooling, the designer has more and more to deal with PCB architecture including high density interconnect (HDI) technology, which relies on small diameter laser drilled micro-vias. Compared with conventional PCB technologies, HDI creates denser interconnect substrates, containing multilevel micro-via structures that play a decisive role in the miniaturization of circuit boards but will exacerbate the component cooling design complexity. To improve the understanding of conventional and future configurations of via structure and their influence on the component thermal performances, a study was leaded on an micro lead frame package, which is now mainstream for both analog and digital functions. For still air conditions, the thermal simulation results show that via and micro-via structures allow to drain more than 90% of the component power through the PCB metallic planes and are mandatory to limit the temperature excess. Thus, the thermal modeling of the latest 3D Integrated Circuit is reinforcing the need to simulate in more thin details its board surrounding architecture as well as its packaging. However, a fine detailed modeling of board layers layout always exceeds the simulation tool capabilities and requires new modeling methodologies able to define the most significant thermal model. Based on DEvelopment of Libraries of PHysIcal models (DELPHI) methodology, the creation of a compact thermal model, compliant to a set of boundary conditions was investigated for a local board area. The thermal behavior prediction, found to be within ± 5% of error, demonstrates the feasibility of extending the boundary condition independence principle to board modeling in order to achieve a more efficient and accurate board cooling optimization.

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