Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, and memory controller has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly nonuniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can affect performance by a factor as much as 30%. In this paper, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. The analysis was performed for 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed. Each functional unit on the die has a specific role, so functional units with similar roles were grouped together. Thus, the actual Pentium IV die was divided into four groups (front end, execution cores, bus and L2, and out-of-order engine). Repositioning constraints were determined using circuit delay models of major functional units in a micro-architectural simulator. Thus, depending on the scenario, relocating functional units can result in virtually no performance loss (less than 2% is assumed to be minimal and is reported as 0%) to as much as 30% performance loss. From the results, the minimum and the maximum temperatures were 56.6°C and 62.2°C. This ΔT corresponds to thermal design power of 60.2 W. For microprocessors with higher thermal design power (115 W) and operating at higher clock speed, higher ΔT can be realized. Based on this paper’s analysis, the optimized scenario resulted in a junction temperature of 56.6°C at the cost of a 14% performance loss.

1.
Borkar
,
S.
, 1999, “
Design Challenges of Technology Scaling
,”
IEEE MICRO
0272-1732,
19
(
4
), pp.
23
29
.
2.
Mahajan
,
R.
, Oct. 2002, “
Thermal Management of CPUs: A Perspective on Trends, Needs and Opportunities
,”
Keynote presentation at the Eighth International Workshop on Thermal Investigations of ICs and Systems SIA
.
3.
2005, International Technology Roadmap for Semiconductors.
4.
Mahajan
,
R.
,
Chiu
,
C. -P.
, and
Chrysler
,
G.
, 2006, “
Cooling a Microprocessor Chip
,”
Proc. IEEE
0018-9219,
94
(
8
), pp.
1476
1486
.
5.
Zhiping
,
Y.
,
Yergeau
,
D.
,
Dutton
,
R.
,
Nakagawa
,
S.
, and
Deeney
,
J.
, 2006, “
Fast Placement-Dependent Full Chip Thermal Simulation
,”
Proceedings of the International Symposium on VLSI Technology, Systems and Applications
, Taipei, Taiwan, pp.
249
552
.
6.
Goh
,
T.
,
Seetharamu
,
K.
,
Quadir
,
G.
, and
Zainal
,
Z.
, 2002, “
Thermal Methodology for Evaluating the Performance of Microelectronic Devices With Non-Uniform Power Dissipation
,”
52nd Electronic Components and Technology Conference
, San Diego, CA, pp.
1181
1186
.
7.
Gektin
,
V.
,
Zhang
,
R.
,
Vogel
,
M.
,
Xu
,
G.
, and
Lee
,
M.
, 2004, “
Substantiation of Numerical Analysis Methodology for CPU Package With Non-Uniform Heat Dissipation and Heat Sink With Simplified Fin Modeling
,”
9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena in Electronic Systems
, ITHERM 2004, pp.
537
542
.
8.
Sikka
,
K.
, 2005, “
An Analytical Temperature Prediction Method for Chip Power Map
,”
Semiconductor Thermal Management and Management Symposium
, pp.
161
166
.
9.
June
,
M.
, and
Sikka
,
K.
, 2002, “
Using Cap-Integral Standoffs to Reduce Chip Hot-Spot Temperature in Electronic Packages
,”
8th Intersociety Conference on Thermal and Thermo-mechanical Phenomena in Electronic Systems
, ITHERM 2002, pp.
173
178
.
10.
Skadron
,
K.
,
Stan
,
M.
,
Huang
,
W.
,
Velusamy
,
S.
,
Sankaranarayanan
,
K.
, and
Tarjan
,
D.
, 2003, “
Temperature-Aware Microarchitecture
,”
Proceedings of the 30th International Symposium on Computer Architecture
, pp.
2
13
.
11.
Kaisare
,
A.
,
Agonafer
,
D.
,
Haji-Sheikh
,
A.
,
Chrysler
,
G.
, and
Mahajan
,
R.
, 2005, “
Thermal Based Optimization of Functional Block Distribution in a Non-Uniformly Powered Die
,”
InterPACK 2005
, San Francisco, CA, pp.
675
682
.
12.
Kaisare
,
A.
,
Agonafer
,
D.
,
Chrysler
,
G.
, and
Mahajan
,
R.
, 2006, “
Design Rule for Minimizing Thermal Resistance in a Non-Uniformly Powered Microprocessors
,”
Semi-Therm
, Dallas, TX, pp.
108
115
.
13.
Karajgikar
,
S.
,
Agonafer
,
D.
,
Ghose
,
K.
,
Sammakia
,
B.
,
Amon
,
C.
, and
Refai-Ahmed
,
G.
, 2009, “
Development of Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance
,”
InterPACK
, San Francisco, CA.
14.
Wu
,
W.
,
Jin
,
L.
,
Yang
,
J.
,
Liu
,
P.
, and
Tan
,
S. X.-D.
, 2006, “
A Systematic Method for Functional Unit Power Estimation in Microprocessors
,”
Design Automation Conference, 43rd ACM/IEEE
, pp.
554
557
.
15.
Source: Dr. Kanad Ghose, SUNY Binghamton.
16.
Zeng
,
H.
,
Yourst
,
M.
,
Ghose
,
K.
, and
Ponomarev
,
D.
, 2009, “
MPTLsim: A Cycle-Accurate, Full-System Simulator for x86-64 Multicore Architectures With Coherent Caches
,”
ACM SIGARCH Computer Architecture News
,
37
(
2
), pp.
1
9
.
18.
Marr
,
D.
,
Binns
,
F.
,
Hill
,
D.
,
Hinton
,
G.
,
Koufaty
,
D.
,
Miller
,
J.
, and
Upton
,
J.
, 2002, “
Hyper-Threading Technology Architecture and Microarchitecture
,”
Intel Technol. J.
1535-864X,
6
(
1
), pp.
4
15
.
19.
Boggs
,
D.
,
Baktha
,
A.
,
Hawkins
,
J.
,
Marr
,
D.
,
Miller
,
J.
,
Roussel
,
P.
,
Singhal
,
R.
,
Toll
,
B.
, and
Venkatraman
,
K.
, 2004, “
The Microarchitecture of the Intel Pentium 4 Processor on 90 nm Technology
,”
Intel Technol. J.
1535-864X,
8
(
1
), pp.
1
18
.
20.
Hennessy
,
J.
, and
Patterson
,
D.
, 1997,
Computer Organization and Design—The Hardware/Software Interface
,
2nd ed.
,
Morgan Kaufmann
,
San Francisco, CA
.
21.
ANSYS ICEPAK, Ver. 4.4.8.
22.
Source: Intel Pentium 4 Processors for Embedded Computing Specifications.
23.
Bar-Cohen
,
A.
,
Kraus
,
A.
, and
Davidson
,
S.
, 1983, “
Thermal Frontiers in the Design and Packaging of Microelectronic Equipment
,”
Mech. Eng. (Am. Soc. Mech. Eng.)
0025-6501,
105
(
6
), pp.
53
59
.
You do not currently have access to this content.