The disturbed state concept (DSC) with the hierarchical single surface (HISS) plasticity model have been proposed and validated previously for a wide range of problems in electronic packaging. In this paper, detailed analyses are performed with the DSC∕HISS model to study the effect of various factors, such as computational and geometrical aspects and material parameters, on the failure life of chip substrate systems. The results and the methodology can be used for parametric analyses and optimal design of problems in electronic packaging.

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