As CMOS transistor gate lengths are scaled below , thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the drain region of the device, which may increase the drain series and source injection electrical resistances. Such trends are accelerated with the introduction of novel materials and nontraditional transistor geometries, like ultrathin body, surround-gate, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomenan including ballistic electron transport, which reshapes the hot spot region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. In this paper we survey trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.
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June 2006
Research Papers
Thermal Phenomena in Nanoscale Transistors
Eric Pop
,
Eric Pop
Department of Electrical Engineering,
Stanford University
, Stanford, CA 94305
Search for other works by this author on:
Kenneth E. Goodson
Kenneth E. Goodson
Department of Mechanical Engineering,
goodson@stanford.edu
Stanford University
, Stanford, CA 94305
Search for other works by this author on:
Eric Pop
Department of Electrical Engineering,
Stanford University
, Stanford, CA 94305
Kenneth E. Goodson
J. Electron. Packag. Jun 2006, 128(2): 102-108 (7 pages)
Published Online: December 14, 2006
Article history
Received:
January 21, 2005
Revised:
December 14, 2006
Citation
Pop, E., and Goodson, K. E. (December 14, 2006). "Thermal Phenomena in Nanoscale Transistors." ASME. J. Electron. Packag. June 2006; 128(2): 102–108. https://doi.org/10.1115/1.2188950
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