Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.
Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 13, 2004; revision received June 23, 2004. Review conducted by: Y. C. Chan.
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Rubinsztajn , S., Buckley , D., Campbell , J., Esler , D., Fiveland , E., Prabhakumar , A., Sherman , D., and Tonapi, S. (June 3, 2005). "Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials ." ASME. J. Electron. Packag. June 2005; 127(2): 77–85. https://doi.org/10.1115/1.1846067
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