One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

Keywords:
chip scale packaging, encapsulation, integrated circuit interconnections, integrated circuit metallisation, flip-chip devices, integrated circuit reliability, laser materials processing, integrated circuit packaging, Wafer Level Packaging, System in Package, Encapsulation, Metallization, Laser Structuring, Duromer MID
Topics:
Lasers, Manufacturing, Packaging, Reliability, Semiconductor wafers, System-in-package, Flip-chip devices, Epoxy adhesives, Epoxy resins
1.
To¨pper, M., Schaldach, M., Fehlberg, S., Karduck, C., Meinherz, C., Heinricht, K., Bader, V., Hoster, L., Coskina, P., Kloeser, A., Ehrmann, O., and Reichl, H., 1998, “Chip Size Package-The Option of Choice for Miniaturized Medical Devices,” IMAPS, USA.
2.
Goodman
,
T.
, and
Elenius
,
P.
,
2004
, “
Wafer-Level Packaging Today
,”
Circuits Assembly
,
15
(
2
), pp.
28
–
32
.
3.
Becker, K.-F., Ghahremani, C., Jung, E., and Neumann, A., 2003, “Rapid Prototyping for Advanced System Integration,” Good Die Newsletter, 14, pp. 28–32; www.gooddie.net.
4.
Schuenemann, M., Amiri Jam, K., Grosser, V., Leutenbauer, R., Bauer, G., Schaefer, W., and Reichl, H., 2000, “MEMS Modular Packaging and Interfaces,” Proc. ECTC 2000, Las Vegas, NV.
5.
Matuscheck, P., Evers, J., Schaefer, W., Nienhaus, M., and Kleen, S., 2002, “A field mill based on the modular MEMS framework MATCH-X,” Proc. Actuator 2002, June 10–12, Bremen, Germany.
6.
Klein, M., Oppermann, H., Aschenbrenner, R., and Reichl, H., 2002, “Modular Systems for Sensor Integration,” Proc. IMAPS 2002 Denver, CO.
7.
Triantafyllou
,
M.
,
Neumann
,
K.-T.
,
Reichl
,
H.
,
Ansorge
,
F.
,
Großer
,
V.
,
Becker
,
K.-F.
,
Schmidt
,
E.
, and
Maier
,
R.
,
1999
, “
Mechatronics for Automotive and Industrial Applications
,”
IEEE Trans. Adv. Packag.
,
22
(
3
), pp.
433
–
441
.
8.
Solberg, V., 2003, “Innovative 3D solutions for multiple die packaging,” Proc. SMTA 2003, Chicago, IL.
9.
Val, C., 2003, “New Approaches to 3D Interconnection Systems in Package Applications,” Proc. IMAPS 2003, Boston, NA.
10.
Boettcher, L., Dombrowski, C., Ostmann, A., and Reichl, H., 2002, “Wafer-level redistribution using fully-additive Cu/Ni/Au metallization,” Proc. SMTA 2002, Chicago, Il.
11.
Jung, E., Aschenbrenner, R., Ostmann, A., Zakel, E., and Reichl, H., 1995, “Flip Chip Soldering and Adhesive Bonding on Organic Substrates,” Proc. JIEMT, Omiya, pp. 67–71.
12.
Cichos, S., 2003, “Radio Frequency Identification (RFID)-Ein U¨berblick vom EAS-Transponder bis zum multifunktionalen Data-Logger,” Seminar Aufbau- und Verbindungstechniken der Mikroelektronik, Technische Universita¨t Berlin, May 15, Berlin.
13.
Braun, T., Becker, K.-F., Koch, M., Bader, V., Oestermann, U., Manessis, D., Aschenbrenner, R., and Reichl, H., 2002, “Wafer Level Encapsulation-A Transfer Molding Approach to System in Package Generation,” Proc. of EPTC 2002, December 10–11, Singapore.
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