The presence of dissimilar material systems and thermal gradients introduces thermal stresses in multi-layered electronic assemblies and packages during fabrication and operation. The thermal stresses of the chip-substrate structure near free edges play an important role in determining the reliability of electronic packaging structures. Therefore, it is important to provide designers a good estimate of free edge stresses. According to the heat conduction mechanism of integrated circuits, the temperature field distribution in the chip and substrate is derived and solved when the chip works in a steady state. Taking the temperature field in the chip and substrate as the heat source, we solve the thermal stress field in the chip and substrate by using the technique of Fourier’s series expansion. The effects of geometric parameters of the chip and substrate on thermal stresses are analyzed. From the analysis of thermal stresses in the chip-substrate structure, it can be found that the stress concentration near free edges is more prominent. In the design of electronic packagings, the stress concentration near free edges which may cause cracking and delamination leading to the failure or malfunction of electronic assemblies and packages should be taken into account in details.
The Thermoelastic Analysis of Chip-Substrate System
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received May 2003; final revision, Jan. 2004. Associate Editor: S. McKeown.
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Wu, L. (October 6, 2004). "The Thermoelastic Analysis of Chip-Substrate System ." ASME. J. Electron. Packag. September 2004; 126(3): 325–332. https://doi.org/10.1115/1.1772413
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