This paper examines the modeling of viscoplastic solder behavior in the vicinity of interfacial cracking for flip chip semiconductor packages. Of particular interest is the relationship between viscoplastic deformation in the solder bumps and any possible interface cracking between the epoxy underfill layer and the silicon die. A 3-D finite element code, developed specifically for the study of interfacial fracture problems, was modified to study how viscoplastic solder material properties would affect fracture parameters such as strain energy release rate and phase angle for nearby interfacial cracks. Simplified two-layer periodic symmetry models were developed to investigate these interactions. Comparison of flip chip results using different solder material models showed that viscoplastic models yielded lower stress and fracture parameters than time independent elastic-plastic simulations. It was also found that adding second level attachment greatly increases the magnitude of the solder strain and fracture parameters. As expected, the viscoplastic and temperature dependent elastic-plastic results exhibited greater similarity to each other than results based solely on linear elastic properties.
Analysis of Interfacial Cracking in Flip Chip Packages With Viscoplastic Solder Deformation
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 2003; final revision, November 2003. Associate Editor: Z. Suo.
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Heffes , M. J., and Nied, H. F. (April 30, 2004). "Analysis of Interfacial Cracking in Flip Chip Packages With Viscoplastic Solder Deformation ." ASME. J. Electron. Packag. March 2004; 126(1): 135–141. https://doi.org/10.1115/1.1649242
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