Due to the CPU limitation of the computer hardware currently available, the three-dimensional full-scaled finite element model of wafer level packaging is impractical for the reliability analysis and fatigue life prediction. In order to significantly reduce the simulation CPU time, an equivalent beam method based on the micro-macro technique with multi-point constraint method is proposed in the present study. The proposed novel equivalent beam consists of three/five sections to simulate the three-dimensional solder joint with different upper/lower pad size. Moreover, the total length of the proposed equivalent beam equals to the stand-of-height of the realistic solder joint. To compare the results of equivalent beam and full-scaled model, a wafer level packaging with 48 I/O is selected as a benchmark model in this study. The result shows that the equivalent beam model can reduce approximately 80 percent CPU time, and good agreement between the equivalent beam model and the full-scaled model are achieved.
Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received November 2002. Associate Editor: L. Ernst.
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Yuan, C., and Chiang, K. (December 15, 2003). "Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging ." ASME. J. Electron. Packag. December 2003; 125(4): 576–581. https://doi.org/10.1115/1.1604159
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