Due to the CPU limitation of the computer hardware currently available, the three-dimensional full-scaled finite element model of wafer level packaging is impractical for the reliability analysis and fatigue life prediction. In order to significantly reduce the simulation CPU time, an equivalent beam method based on the micro-macro technique with multi-point constraint method is proposed in the present study. The proposed novel equivalent beam consists of three/five sections to simulate the three-dimensional solder joint with different upper/lower pad size. Moreover, the total length of the proposed equivalent beam equals to the stand-of-height of the realistic solder joint. To compare the results of equivalent beam and full-scaled model, a wafer level packaging with 48 I/O is selected as a benchmark model in this study. The result shows that the equivalent beam model can reduce approximately 80 percent CPU time, and good agreement between the equivalent beam model and the full-scaled model are achieved.

Issue Section:
Technical Papers
Keywords:
circuit simulation, integrated circuit packaging, soldering, fatigue, integrated circuit reliability, integrated circuit modelling
Topics:
Packaging, Semiconductor wafers, Simulation, Solder joints, Shear (Mechanics), Finite element analysis, Thermomechanics, Materials properties, Fatigue life, Finite element model, Modeling
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