This research concerns itself with a stress and reliability analysis of electronic packages with ultra-thin chips based on the finite element method. The effect of chip and substrate thickness, substrate material, presence of underfill, dimensions, and shape of the bump on stress reduction is analyzed. Obtained results clearly show that chip thinning, when used with an appropriate design of the entire package, can significantly decrease stresses and stress intensity factors and improve the reliability of the package. The developed software provides an effective design tool to quantify the reliability, stresses, and deflections of a package with ultra-thin chips.
Stress and Reliability Analysis of Electronic Packages With Ultra-Thin Chips
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EPPD Division, October 1, 2001. Associate Editor: B. Michel.
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Shkarayev, S., Savastiouk, S., and Siniaguine, O. (March 14, 2003). "Stress and Reliability Analysis of Electronic Packages With Ultra-Thin Chips ." ASME. J. Electron. Packag. March 2003; 125(1): 98–103. https://doi.org/10.1115/1.1535932
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