The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder interconnection, such as wire interconnect technology (WIT). New technology, which uses copper posts to replace the solder bumps as interconnections, has improved reliability. Moreover, this type of wafer level package produces higher I/O density, as well as ultra fine pitch. This research focuses on the reliability analysis, material selection and structural design of WIT packaging. This research employs finite element method (FEM) to analyze the physical behavior of packaging structures under thermal cycling conditions to compare the reliability characteristics of conventional wafer level and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature-dependent material properties will be applied to all models.
Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EPPD April 3, 2001. Associate Editor: B. Courtois.
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Lin, Y. T., Peng, C. T., and Chiang, K. N. (July 26, 2002). "Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging ." ASME. J. Electron. Packag. September 2002; 124(3): 234–239. https://doi.org/10.1115/1.1481368
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