The reduction of the warpage of LSI package is a critical issue to ensure good solder joint connection in surface mount. In this study, different combinations of finite element and calculating methods were used to investigate the best method for predicting the thin small outline packages (TSOP) warpage. The results indicate that viscoelastic-GK calculation with relaxation of shear modulus and of bulk modulus using the multilayer shell element is the most appropriate method for predicting the warpage. All calculations confirm that a compound thickness ratio of 1.2 results in minimal warpage for a large chip TSOP. In this case, the warpage is reduced to near zero and the compound properties have little influence on warpage. However, for a small chip TSOP, a compound thickness ratio of 2.0–2.9 reduces the warpage. The warpage of small chip TSOP shows a severe saddle shape. The ratio and the magnitude of warpage depend on the compound properties. Also, the elastic method may result in a false simulation.
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e-mail: kiyoshi_miyake@gg.nitto.co.jp
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June 2001
Technical Papers
Viscoelastic Warpage Analysis of Surface Mount Package
Kiyoshi Miyake,
e-mail: kiyoshi_miyake@gg.nitto.co.jp
Kiyoshi Miyake
Reliability Evaluation Center, Nitto Denko Corporation, Kameyama, Mie, 519-0193 Japan
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Tsukasa Yoshida,
Tsukasa Yoshida
Reliability Evaluation Center, Nitto Denko Corporation, Kameyama, Mie, 519-0193 Japan
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Hyung Gil Baik,
e-mail: hkbaig@hei.co.kr
Hyung Gil Baik
Package Development Dept., Hyundai Electronics Inc., Ichon-si, Kyoungki-do, 467-701, Korea
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Sang Wook Park
Sang Wook Park
Package Development Dept., Hyundai Electronics Inc., Ichon-si, Kyoungki-do, 467-701, Korea
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Kiyoshi Miyake
Reliability Evaluation Center, Nitto Denko Corporation, Kameyama, Mie, 519-0193 Japan
e-mail: kiyoshi_miyake@gg.nitto.co.jp
Tsukasa Yoshida
Reliability Evaluation Center, Nitto Denko Corporation, Kameyama, Mie, 519-0193 Japan
Hyung Gil Baik
Package Development Dept., Hyundai Electronics Inc., Ichon-si, Kyoungki-do, 467-701, Korea
e-mail: hkbaig@hei.co.kr
Sang Wook Park
Package Development Dept., Hyundai Electronics Inc., Ichon-si, Kyoungki-do, 467-701, Korea
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received at ASME Headquarters September 25, 2000. Associate Editor: D. Read.
J. Electron. Packag. Jun 2001, 123(2): 101-104 (4 pages)
Published Online: June 1, 2001
Citation
Miyake, K., Yoshida, T., Baik, H. G., and Park, S. W. (June 1, 2001). "Viscoelastic Warpage Analysis of Surface Mount Package ." ASME. J. Electron. Packag. June 2001; 123(2): 101–104. https://doi.org/10.1115/1.1339820
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