In multi-layer printed wiring boards (PWBs), electrical connections between different layers are accomplished with plated through holes (PTHs). The reliability of the PTH barrel and the PTH-inner plane (IP) connection depends not only on the design but also on the conditions of manufacturing and assembly processes of the board. The concerns associated with manufacturing arise from drilling which heats up and smears the surrounding epoxy onto the copper inner plane surfaces and also from subsequent chemical hole-clean operations which desmear the drilled holes. Good adhesion of the PTH copper to the desmeared PTH wall and to the copper inner planes is important for the reliability of the PTHs during assembly and field service. PWB coupons consisting of resin-glass bundle areas as well as resin filled clearance areas surrounding the PTH have been considered for a series of experiments and tests. On these coupons, accelerated stress tests and failure analysis of the PTHs at the end of these tests have been conducted. An elasto-plastic finite element analysis of the PTH strains for a temperature excursion of 102°C has been carried out for signal PTHs without and with IP connections. A peel test, using a micro-mechanical tester, has also been carried out to assess the adhesion of PTH copper to different regions along the drilled hole. All of the testing techniques have been supplemented by suitable analytical techniques for studying the distribution of smear on the copper inner planes. A birefringence technique to estimate the temperature of the hole wall during drilling has been described. All of the fails observed during stress testing are in the form of cracks in the PTH barrel, the plane of the crack being perpendicular to the barrel axis. The cracks are localized near the glass bundle-resin rich interface. It has also been observed in the failure analysis that the PTH/IP connections are not susceptible to failure during the accelerated stress testing conditions considered. These observations are also supported by the results of stress analysis. The results of stress analysis show that the interior clearance holes show higher strains than those closer to board surfaces, suggesting that the PTH barrel failure is likely to occur at the clearance hole and that the likelihood of failure at the interior clearance holes is higher than those closer to the PWB surfaces. The results of the peel test reveal that in the glass bundle-resin regions, the adhesion along the PTH wall is determined by the mechanical interlocking between the plated copper and the glass bundles and is relatively insensitive to desmear operations. However, adhesion in the resin-rich areas is a strong function of the desmear operation, which enhances the adhesion of the PTH to the resin. Finally, it is shown that the birefringence technique may be used effectively to estimate the drilling temperature and, hence, the degree of smearing and PTH quality. It is concluded that while smear may play an important role in the failure of PTHs in PWBs, for thick packaging boards with high aspect ratio PTHs, the predominant failure mechanism is less likely to be smear related. Such a failure mechanism would be preceded by failure in the PTH barrels as a result of the large strain concentrations imposed at specific locations within the cross-section.

Issue Section:
Technical Papers
Keywords:
printed circuit manufacture, packaging, finite element analysis, stress analysis, failure analysis
Topics:
Copper, Double refraction, Drilling, Drills (Tools), Epoxy resins, Failure, Failure analysis, Finite element analysis, Fracture (Materials), Glass, Manufacturing, Printed circuit boards, Resins, Signals, Stress, Stress analysis (Engineering), Temperature, Testing, Clearance holes, Adhesion, Packaging, Reliability
1.
Markovich, V. R., and Poch, F. S., 1989, “Plated Through Hole Technology,” Principles of Electronic Packaging, Seraphim, D. P., Lasky, R., and Li, C-Y., eds., McGraw-Hill, New York, NY, pp. 519–538.
2.
Oien, M. A., 1976, “A Simple Model for the Thermomechanical Deformation of Plated-Through-Holes in Multilayer Printed Wiring Boards,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by IEEE Electron Device Soc., and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 121–128.
3.
Oien, M. A., 1976, “Methods for Evaluating Plated-Through-Hole Reliability,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by IEEE Electron Device Soc., and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 129–131.
4.
Barker
,
D.
,
Pecht
,
M.
,
Dasgupta
,
A.
, and
Naqvi
,
S.
,
1991
, “
Transient Thermal Stress Analysis of a Plated Through Hole Subjected to Wave Soldering
,”
ASME J. Electron. Packag.
,
113
, No.
2
, pp.
149
–
155
.
5.
Barker, D., and Dasgupta, A., 1993, “Thermal Stress Issues in Plated-Through-Hole Reliability,” Thermal Stress and Strain in Microelectronics Packaging, Lau, J. H., ed., van Nostrand Reinhold, New York, NY, pp. 648–683.
6.
Vecchio
,
K. S.
, and
Hertzberg
,
R. W.
,
1988
, “
Analysis of Long Term Reliability of Plated Through Holes in Multilayer Interconnection Boards Part A: Stress Analysis and Material Characterization
,”
Microelectron. Reliab.
,
26
, No.
4
, pp.
715
–
732
.
7.
Kurosawa, K., Takeda, Y., Takaji, K., and Kawamata, H., 1981, “An Investigation of Reliability Behavior of Plated Through Holes in Multilayer Printed Wiring Boards,” IPC Technical Paper, IPC-TP-385, Inst. for Interconnecting and Packaging Electronic Circuits, Lincolnwood, IL, pp. 1–13.
8.
Mirman
,
B. A.
,
1988
, “
Mathematical Model of Plated Through Hole Under a Load Induced by Thermal Mismatch
,”
IEEE Trans. Compon., Hybrids, Manuf. Technol.
,
11
, No.
4
, pp.
506
–
511
.
9.
Ozmat, B., Walker, H. and Elkins, M., 1990, “A nonlinear thermal strain analysis of the plated through holes of printed wiring boards,” Proc. of the Technical Conf., Intl. Electronic Packaging Conf., Marlborough, MA, Sep. 10–12, pp. 359–381.
10.
Bhandarkar
,
S. M.
,
Dasgupta
,
A.
,
Barker
,
D.
,
Pecht
,
M.
, and
Engelmaier
,
W.
,
1991
, “
Influence of Selected Design Variables on Thermo-Mechanical Stress Distribution in Plated-Through-Hole Structures
,”
ASME J. Electron. Packag.
,
114
, No.
1
, pp.
8
–
13
.
11.
Iannuzelli, R. J., 1991, “Predicting Plated Through Hole Reliability in High Temperature Manufacturing Processes,” Proc. of the 41st Electronic Components & Technology Conf., Atlanta, GA, IEEE CHMT Society, pp. 410–421.
12.
Ramakrishna, K., Subbarayan, G., and Sammakia, B. G., 1992, “Effect of Non-Uniformities and Defects on PTH Strain during Assembly and Accelerated Thermal Cycling,” Proc. of the First ASME/JSME Joint Electronic Packaging Conf., Chen, W. T., and Abe, H., eds., EEP-Vol. 1, Published by Electronic Packaging Division, ASME, New York, NY, organized by ASME/JSME, Milpitas, CA, April 9–12, pp. 891–909.
13.
Ramakrishna, K., Chen, W. T., Thiel, G. H., Steinwall, J. E., and Niu, T. M., 1994, “Plated Through Holes in Thick Printed Wiring Boards: Interaction Between Design, Materials and Assembly Processes,” Mechanics and Materials for Electronic Packaging: Vol. 1: Design and Process Issues in Electronic Packaging, Chen, W. T., Nguyen, L. T., and Winterbottom, W. L., eds., AMD-Vol. 195, pp. 1–10, 1994 ASME International Mechanical Engineering Congress and Conference, held in Chicago, IL, Nov. 6–11, 1994.
14.
Ramakrishna, K., Thiel, G. H., and Sammakia, B. G., 1997 “Analysis of Thermo-mechanical Stresses and Strains Induced in the Plated Through Holes in Thick Advanced Printed Wiring Boards,” Advances in Electronic Packaging 1997, E. Suhir, M. Shiratori, Y. C. Lee, and G. Subbarayan, eds., Proc. of the INTERpack ’97, an International Electronic Packaging Conf. held in Mauna Lani, Hawaii, June 15–19, EEP-Vol. 19-2, pp. 1639–1646.
15.
Subbarayan
,
G.
,
Ramakrishna
,
K.
, and
Sammakia
,
B. G.
,
1997
, “
The Impact of Interfacial Adhesion on PTH and Via Reliability
,”
ASME J. Electron. Packag.
,
119
, No.
4
, pp.
260
–
267
.
16.
Ammann, H. H., and Jocher, R. W., 1976, “Measurement of Thermo-Mechanical Strain in Plated Through Holes,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by the IEEE Electron Devices Society, and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 118–120.
17.
Tossell
,
D. A.
, and
Ashbee
,
K. H. G.
,
1989
, “
High Resolution Optical Interference Investigation of Deformation Due to Thermal Expansion Mismatch Around Plated Through Holes In Multilayer Circuit Boards
,”
J. Electron. Mater.
,
18
, No.
2
, pp.
275
–
286
.
18.
Ashbee
,
K. H. G.
, and
Tossell
,
D. A.
,
1989
, “
Internal Stresses Adjacent to a Hole Through a Multilayer Wiring Board
,”
J. Adhes.
,
29
, Nos.
1–4
, pp.
131
–
140
.
19.
Gross, T. S., Watt, D. W., and Hening, S. D., 1990, “Thermally Induced Displacement Field Around Plated Through Holes on a Constrained Coefficient of Expansion Printed Wiring Board Measured by Holographic Interferometry,” Proc. of the Technical Conf., Intl. Electronic Packaging Conf., Marlborough, MA, Sept. 10–12, pp. 165–178.
20.
Gross
,
T. S.
,
Perault
,
J. A.
, and
Watt
,
D. W.
,
1994
, “
An Experimental Investigation of Deformation of Plated Holes for a Single 30-210-30°C Thermal Cycle
,”
ASME J. Electron. Packag.
,
116
, No.
3
, pp.
1
–
5
.
21.
Lee
,
L. C.
,
Darekar
,
V. S.
, and
Lim
,
C. K.
,
1984
, “
Micromechanisms of Multilayer Printed Circuit Boards
,”
IBM J. Res. Dev.
,
28
, No.
6
, pp.
711
–
718
.
22.
Anon, 1994, Product information published by IBM Microelectronics Division, 1701 North Street, Endicott, NY.
23.
Takagi, K., and Kobayashi, T., 1990, “Reliability Evaluation of Interconnections using Plated Through Hole with Resin Smear in Multilayer Printed Boards,” Technical Paper B2/1, Proc. of Printed Circuit World Convention, UK, June.
24.
Niu, T. M., Burke, E. J., Black, W. E., and Case, J. R., 1992, “6-axis Submicron Fatigue Tester,” Proc. of the First ASME/JSME Joint Electronic Packaging Conf., Chen, W. T., and Abe, H., eds., EEP-Vol. 1, Published by Electronic Packaging Division, ASME, New York, NY, organized by ASME/JSME, Milpitas, CA (April 9–12, 1992), pp. 937–945.
25.
Weiss
,
R. E.
,
1977
, “
The Effect of Drilling Temperature on Multilayer Board Hole Quality
,”
Circ. World
,
3
, pp.
8
–
14
.
26.
Hagge
,
J. K.
,
1977
, “
Drilling Multilayer Glass-PTFE Circuit Boards
,”
Circ. World
,
3
, p.
8
8
.
27.
Tuck, J., 1983, “Small-hole Drilling,” Circuits Manufacturing, Feb.
28.
Murray, J., 1984, “Challenges in Drilling,” Circuits Manufacturing, Oct.
29.
Murray, J., 1984, “On Drilling,” Circuit Manufacturing, Dec.
30.
Berlin, A. J., 1985, “Excessive Drilling Heat Leads to Board Failures,” Electronic Packaging and Production, Jan., p. 168.
31.
Vega-Marchena, Z., 1987, “An Investigation of Multilayer Printed Circuit Board Drill Smear,” Ph.D. dissertation, Dept. of Mech. Eng., Univ. of Texas, Austin, TX.
32.
Kramer
,
E. J.
,
Chen
,
W. T.
, and
Strope
,
D. H.
,
1990
, “
Birefringence in Epoxy Glass Laminates Due to Hole Drilling,” IBM Internal Report, Microelectronics Division, IBM Corporation, Endicott, NY.
33.
Anon, 1994, “LATEST: Circuit Reliability Tester,” Product information, IBM Microelectronics Division, 1701 North Street, Endicott, NY.
34.
Anon, 1996, “ANSYS Engineering Analysis System User’s Manual,” Revision 5.3, ANSYS, Inc., Cannonsburg, PA.
35.
Wu
,
T. Y.
,
Guo
,
Y.
, and
Chen
,
W. T.
,
1993
, “
Thermal-Mechanical Strain Characterization for Printed Wiring Boards
,”
IBM J. Res. Dev.
,
37
, No.
5
, pp.
621
–
634
.
36.
Carslaw, H. S., and Jaeger, J. C., 1959, Conduction of Heat in Solids, 2nd Ed., Oxford Univ. Press, Oxford, U.K., pp. 188–213.
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