In this paper, methods to analyze the flow during semiconductor chip encapsulation have been developed. A numerical method is used for the flow analysis in the chip cavity. In this study, for accurate analysis of flow in the chip cavity, models for the cross flow through the leadframe openings have been developed. The models have been verified by comparing with two experiments. In the first experiment, clear polymer and transparent mold have been used for the visualization of flow in a cavity with a leadframe. In the next experiment, actual epoxy molding compound together with an industrial encapsulation process have been used to observe the melt-front advancement shapes. The calculated and experimental results show good agreement. [S1043-7398(00)00902-6]
Flow Analysis in a Chip Cavity During Semiconductor Encapsulation
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD November 5, 1997; revised manuscript received January 11, 1999. Associate Technical Editor: Y. Joshi.
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Han , S., and Wang, K. K. (January 11, 1999). "Flow Analysis in a Chip Cavity During Semiconductor Encapsulation ." ASME. J. Electron. Packag. June 2000; 122(2): 160–167. https://doi.org/10.1115/1.483149
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