A bare, four copper layer printed wiring board with simple trace patterns was built for modeling and experimental validation purposes. In-plane elastic properties of the core materials in the board were measured as a function of temperature. Thermoelastic lamination theory was utilized to predict the warpage of the board when subjected to an infrared reflow process, with emphasis on studying the influence of thermal gradients through the board, its support conditions and CTE differential on the warpage process. Board layers with traces were approximated with quasi-homogeneous effective properties obtained using micromechanics theory. An experimental system that employs the shadow moird technique in a simulated infrared reflow environment was used to evaluate the warpage for comparison to modeled results.
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December 1999
Technical Papers
Thermoelastic Modeling of a PWB With Simulated Circuit Traces Subjected to Infrared Reflow Soldering With Experimental Validation
Y. Polsky,
Y. Polsky
School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
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I. C. Ume
I. C. Ume
School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
Search for other works by this author on:
Y. Polsky
School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
I. C. Ume
School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405
J. Electron. Packag. Dec 1999, 121(4): 263-270 (8 pages)
Published Online: December 1, 1999
Article history
Received:
January 1, 1999
Revised:
May 5, 1999
Online:
November 5, 2007
Citation
Polsky, Y., and Ume, I. C. (December 1, 1999). "Thermoelastic Modeling of a PWB With Simulated Circuit Traces Subjected to Infrared Reflow Soldering With Experimental Validation." ASME. J. Electron. Packag. December 1999; 121(4): 263–270. https://doi.org/10.1115/1.2793850
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