The effect of underfill material on reliability of flip chip on board (FCOB) assemblies is investigated in this study by using two-dimensional and three-dimensional finite element simulations under thermal cycling stresses from −55°C to 80°C. Accelerated testing of FCOB conducted by the authors reveals that the presence of underfill can increase the fatigue durability of solder interconnects by two orders of magnitude. Similar data has been extensively reported in the literature. It is the intent of this paper to develop a generic and fundamental predictive model that explains this trend. While empirical models have been reported by other investigators based on experimental data, the main drawback is that many of these empirical models are not truly predictive, and can not be applied to different flip chip architectures using different underfills. In the proposed model, the energy-partitioning (EP) damage model is enhanced in order to capture the underlying mechanisms so that a predictive capability can be developed. A two-dimensional finite element model is developed for stress analysis. This model accounts for underfill over regions of solder in an approximate manner by using overlay elements, and is calibrated using a three-dimensional finite element model. The model constant for the enhanced EP model is derived by fitting model predictions (combination of two-dimensional and three-dimensional model results) to experimental results for a given temperature history. The accuracy of the enhanced EP model is then verified for a different loading profile. The modeling not only reveals the influence of underfill material on solder joint durability, but also provides the acceleration factor to assess durability under life cycle environment, from accelerated test results. Experimental results are used to validate the trends predicted by the analytical model. The final goal is to define the optimum design and process parameters of the underfill material in FCOB assemblies in order to extend the fatigue endurance of the solder joints under cyclic thermal loading environments.

1.
ABAQUS, 1997, Version 5.7, Theory and Users Manual, Hibbitt, Karlsson & Sorenson, Inc., RI.
2.
Baggerman
A. F. J.
,
Caers
J. F. J. M.
,
Wondergem
J. J.
, and
Wagemans
A. G.
,
1996
, “
Low-Cost-Flip-Chip on Board
,”
IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B
, Vol.
19
, No.
4
, pp.
736
746
.
3.
Darbha, K., Okura, J. H., Dasgupta, A., and Caers, J. F. J. M., 1997, “Thermo-mechanical Durability Analysis of Flip Chip Solder Interconnects Without Underfill,” Proceedings, ASME Winter Annual Conference: 9th Symposium on Mechanics of Surface Mount Assemblies, November 1997, Dallas, TX.
4.
Dasgupta
A.
,
Oyan
C.
,
Barker
D.
, and
Pecht
M.
,
1992
, “
Solder Creep-Fatigue Analysis by an Energy-Partitioning Approach
,”
ASME JOURNAL OF ELECTRONIC PACKAGING
, Vol.
114
, pp.
152
160
.
5.
Doi, H., Kawano, K., and Yasukawa, A., 1997, “Reliability of Underfill-Encapsulated Flip-Chip Packages,” Proceedings, Application of Fracture Mechanics in Electronic Packaging, AMD-Vol. 222/EEP-Vol. 20, ASME, New York.
6.
Doi
K.
,
Hirano
N.
,
Okada
T.
,
Hiruta
Y.
,
Sudo
T.
, and
Mukai
M.
,
1996
, “
Prediction of Thermal Fatigue for Encapsulated Flip Chip Interconnection
,”
Microcircuits and Electronic Packaging
, Vol.
19
, No.
3
, pp.
231
237
.
7.
Le Gall, A. C., Qu, J., and McDowell, D., 1997, “Some Mechanics Issues Related to the Thermomechanical Reliability of Flip Chip DCA With Underfill Encapsulation,” Proceedings, ASME Symposium on Application of Fracture Mechanics in Electronic Packaging, AMD-Vol. 222/EEP-Vol. 20, pp. 85–95.
8.
Okura, J. H., Darbha, K., Dasgupta, A., 1998, “Effect of Underfill in Flip Chip on Board Assemblies,” paper presented at the ASME Winter Annual Conference, 1998, Anahein, CA.
9.
Ramakrishna, K., and Johnson, Z., 1997, “Effect of Material and Design Parameters on the Stresses Induced in a Direct-Chip-Attach Package During Underfill Cure,” ASME InterPACK’97, EEP-Vol. 19-2, ASME, New York, pp. 1639–1646.
10.
Steinberg, D. S., 1988, Vibration Analysis for Electronic Equipment, John Wiley & Sons, New York.
11.
Wang
J.
,
Qian
Z.
, and
Liu
S.
,
1998
, “
Process Induced Stresses of a Flip Chip Packaging by Sequential Processing Modeling Technique
,”
ASME JOURNAL OF ELECTRONIC PACKAGING
, Vol.
120
, pp.
309
313
.
12.
Wong, T. E., 1998, Personal communication.
This content is only available via PDF.
You do not currently have access to this content.