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ASME Press Select Proceedings
International Conference on Advanced Computer Theory and Engineering (ICACTE 2009)
By
Xie Yi
Xie Yi
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ISBN:
9780791802977
No. of Pages:
2012
Publisher:
ASME Press
Publication date:
2009

Prefetching is a common technique of tolerating the memory latency. However, it rapidly increases the communications traffic between the upper-level storage and the lower-level. Based on the analysis of access patterns of the SPEC benchmarks, we propose a novel push structure, in which the L2 cache can actively push instructions and data to the L1 cache at a proper time without the request from the L1 cache. By using a cycle-accurate simulator running SPEC benchmarks, the experimenting results showed that our push structure can significantly reduce the access to the L2 cache by 34.6%. Therefore, our push structure can effectively reduce the communications traffic between the L1 and the L2 cache. Our push structure also averagely increases the IPC by 6.6%.

Abstract
Key Words
1. Introduction
2. Related Work
3. The Sequential Push Structure
4. Experimental Setup
5. Determination of Buffer Depth
6. Experimental Results and Analysis
7. Conclusions
References
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